-- MySQL dump 10.10 -- -- Host: localhost Database: Grayscale-Opcode-DB -- ------------------------------------------------------ -- Server version 5.0.22-Debian_0ubuntu6.06.3-log /*!40101 SET @OLD_CHARACTER_SET_CLIENT=@@CHARACTER_SET_CLIENT */; /*!40101 SET @OLD_CHARACTER_SET_RESULTS=@@CHARACTER_SET_RESULTS */; /*!40101 SET @OLD_COLLATION_CONNECTION=@@COLLATION_CONNECTION */; /*!40101 SET NAMES utf8 */; /*!40103 SET @OLD_TIME_ZONE=@@TIME_ZONE */; /*!40103 SET TIME_ZONE='+00:00' */; /*!40014 SET @OLD_UNIQUE_CHECKS=@@UNIQUE_CHECKS, UNIQUE_CHECKS=0 */; /*!40014 SET @OLD_FOREIGN_KEY_CHECKS=@@FOREIGN_KEY_CHECKS, FOREIGN_KEY_CHECKS=0 */; /*!40101 SET @OLD_SQL_MODE=@@SQL_MODE, SQL_MODE='NO_AUTO_VALUE_ON_ZERO' */; /*!40111 SET @OLD_SQL_NOTES=@@SQL_NOTES, SQL_NOTES=0 */; -- -- Table structure for table `IA-x86` -- DROP TABLE IF EXISTS `IA-x86`; CREATE TABLE `IA-x86` ( `index` bigint(20) NOT NULL auto_increment, `opcode` varchar(100) NOT NULL, `instruction` varchar(100) NOT NULL, `dstOperand` varchar(100) NOT NULL, `srcOperand` varchar(100) NOT NULL, `thirdOperand` varchar(100) NOT NULL, `64bit` varchar(100) NOT NULL, `compatLeg` varchar(100) NOT NULL, `VMX` tinyint(1) NOT NULL, `description` varchar(3000) NOT NULL, PRIMARY KEY (`index`) ) ENGINE=MyISAM DEFAULT CHARSET=latin1; -- -- Dumping data for table `IA-x86` -- /*!40000 ALTER TABLE `IA-x86` DISABLE KEYS */; LOCK TABLES `IA-x86` WRITE; INSERT INTO `IA-x86` VALUES (1,'37','AAA','','','','Invalid','Valid',0,'ASCII adjust AL after addition.'),(2,'D5 0A','AAD','','','','Invalid','Valid',0,'ASCII adjust AX before division.'),(3,'D5 ib','(No mnemonic) D5 ib (AAD)','','','','Invalid','Valid',0,'Adjust AX before division to\r\nnumber base imm8.'),(4,'D4 0A','AAM','','','','Invalid','Valid',0,'ASCII adjust AX after multiply.'),(5,'D4 ib','(No mnemonic) D4 ib (ADD)','','','','Invalid','Valid',0,'Adjust AX after multiply to number\r\nbase imm8.'),(6,'3F','AAS','','','','Invalid','Valid',0,'ASCII adjust AL after subtraction.'),(7,'14 ib','ADC','AL','imm8','','Valid','Valid',0,'Add with carry imm8 to AL.'),(8,'15 iw','ADC','AX','imm16','','Valid','Valid',0,'Add with carry imm16 to AX.'),(9,'15 id','ADC','EAX','imm32','','Valid','Valid',0,'Add with carry imm32 to EAX.\r\nADC EAX,\r\nimm32'),(11,'80 /2 ib','ADC','r/m8','imm8','','Valid','Valid',0,'Add with carry imm8 to r/m8.'),(10,'REX.W + 15 id','ADC','RAX','imm32','','Valid','N.E.',0,'Add with carry imm32 sign extended to 64-bits to RAX.\r\n'),(12,'REX + 80 /2 ib','ADC','r/m8','imm8','','Valid','N.E.',0,'Add with carry imm16 to r/m16.'),(13,'81 /2 id','ADC','r/m32','imm32','','Valid','Valid',0,'Add with CF imm32 to r/m32.'),(14,'REX.W + 81 /2 id','ADC','r/m64','imm32','','Valid','N.E.',0,'Add with CF imm32 sign'),(15,'83 /2 ib','ADC','r/m16','imm8','','Valid','Valid',0,'Add with CF sign-extended'),(16,'83 /2 ib','ADC','r/m32','imm8','','Valid','Valid',0,'Add with CF sign-extended'),(17,'REX.W + 83 /2 ib','ADC','r/m64','imm8','','Valid','N.E.',0,'Add with CF sign-extended'),(18,'10 /r','ADC','r/m8','r8','','Valid','Valid',0,'Add with carry byte register to'),(19,'REX + 10 /r','ADC','r/m8','r8','','Valid','N.E.',0,'Add with carry byte register to'),(20,'11 /r','ADC','r/m16','r16','','Valid','Valid',0,'Add with carry r16 to r/m16.'),(21,'11 /r','ADC','r/m32','r32','','Valid','Valid',0,'Add with CF r32 to r/m32.'),(22,'REX.W + 11 /r','ADC','r/m64','r64','','Valid','N.E.',0,'Add with CF r64 to r/m64.'),(23,'12 /r','ADC','r8','r/m8','','Valid','Valid',0,'Add with carry r/m8 to byte'),(24,'REX + 12 /r','ADC','r8','r/m8','','Valid','N.E.',0,'Add with carry r/m64 to byte'),(25,'13 /r','ADC','r16','r/m16','','Valid','Valid',0,'Add with carry r/m16 to r16.'),(26,'13 /r','ADC','r32','r/m32','','Valid','Valid',0,'Add with CF r/m32 to r32.'),(27,'04 ib','ADD','AL','imm8','','Valid','Valid',0,'Add imm8 to AL.'),(28,'05 iw','ADD','AX','imm16','','Valid','Valid',0,'Add imm16 to AX.'),(29,'05 id','ADD','EAX','imm32','','Valid','Valid',0,'Add imm32 to EAX.'),(30,'REX.W + 05 id','ADD','RAX','imm32','','Valid','N.E.',0,'Add imm32 signextended'),(31,'80 /0 ib','ADD','r/m8','imm8','','Valid','Valid',0,'Add imm8 to r/m8.'),(32,'81 /0 iw','ADD','r/m16','imm16','','Valid','Valid',0,'Add imm16 to r/m16.'),(33,'81 /0 id','ADD','r/m32','imm32','','Valid','Valid',0,'Add imm32 to r/m32.'),(34,'REX.W + 81 /0 id','ADD','r/m64','imm32','','Valid','N.E.',0,'Add imm32 signextended'),(35,'83 /0 ib','ADD','r/m16','imm8','','Valid','Valid',0,'Add sign-extended'),(36,'83 /0 ib','ADD','r/m32','imm8','','Valid','Valid',0,'Add sign-extended'),(37,'REX.W + 83 /0 ib','ADD','r/m64','imm8','','Valid','N.E.',0,'Add sign-extended'),(38,'00 /r','ADD','r/m8','r8','','Valid','Valid',0,'Add r8 to r/m8.'),(39,'REX + 00 /r','ADD','r/m8','r8','','Valid','N.E.',0,'Add r8 to r/m8.'),(40,'01 /r','ADD','r/m16','r16','','Valid','Valid',0,'Add r16 to r/m16.'),(41,'01 /r','ADD','r/m32','r32','','Valid','Valid',0,'Add r32 to r/m32.'),(42,'02 /r','ADD','r8','r/m8','','Valid','Valid',0,'Add r/m8 to r8.'),(43,'REX + 02 /r','ADD','r8','r/m8','','Valid','N.E.',0,'Add r/m8 to r8.'),(44,'03 /r','ADD','r16','r/m16','','Valid','Valid',0,'Add r/m16 to r16.'),(45,'03 /r','ADD','r32','r/m32','','Valid','Valid',0,'Add r/m32 to r32.'),(46,'66 0F 58 /r','ADDPD','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed double-precision floatingpoint'),(47,'0F 58 /r','ADDPS','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed single-precision'),(48,'F2 0F 58 /r','ADDSD','xmm1','xmm2/m64','','Valid','Valid',0,'Add the low doubleprecision'),(49,'F3 0F 58 /r','ADDSS','xmm1','xmm2/m32','','Valid','Valid',0,'Add the low singleprecision'),(50,'66 0F D0 /r','ADDSUBPD','xmm1','xmm2/m128','','Valid','Valid',0,'Add/subtract'),(51,'F2 0F D0 /r','ADDSUBPS','xmm1','xmm2/m128','','Valid','Valid',0,'Add/subtract singleprecision'),(52,'24 ib','AND','AL','imm8','','Valid','Valid',0,'AL AND imm8.'),(53,'25 iw','AND','AX','imm16','','Valid','Valid',0,'AX AND imm16.'),(54,'25 id','AND','EAX','imm32','','Valid','Valid',0,'EAX AND imm32.'),(55,'REX.W + 25 id','AND','RAX','imm32','','Valid','N.E.',0,'RAX AND imm32 signextended'),(56,'80 /4 ib','AND','r/m8','imm8','','Valid','Valid',0,'r/m8 AND imm8.'),(57,'REX + 80 /4 ib','AND','r/m8','imm8','','Valid','N.E.',0,'r/m64 AND imm8 (signextended).'),(58,'81 /4 iw','AND','r/m16','imm16','','Valid','Valid',0,'r/m16 AND imm16.'),(59,'81 /4 id','AND','r/m32','imm32','','Valid','Valid',0,'r/m32 AND imm32.'),(60,'REX.W + 81 /4 id\r\n','AND','r/m64','imm32','','Valid','N.E.',0,'r/m64 AND imm32 sign'),(61,'83 /4 ib','AND','r/m16','imm8','','Valid','Valid',0,'r/m16 AND imm8 (signextended).'),(62,'REX.W + 83 /4 ib','AND','r/m64','imm8','','Valid','N.E.',0,'r/m64 AND imm8 (signextended).'),(63,'20 /r','AND','r/m8','r8','','Valid','Valid',0,'r/m8 AND r8.'),(64,'REX + 20 /r','AND','r/m8','r8','','Valid','N.E.',0,'r/m64 AND r8 (signextended).'),(65,'21 /r','AND','r/m16','r16','','Valid','Valid',0,'r/m16 AND r16.'),(66,'21 /r','AND','r/m32','r32','','Valid','Valid',0,'r/m32 AND r32.'),(67,'REX.W + 21 /r','AND','r/m64','r64','','Valid','N.E.',0,'r/m64 AND r32.'),(68,'REX.W + 21 /r','AND','r/m64','r64','','Valid','N.E.',0,'r/m64 AND r32.'),(69,'22 /r','AND','r8','r/m8','','Valid','Valid',0,'r8 AND r/m8.'),(70,'REX + 22 /r','AND','r8','r/m8','','Valid','N.E.',0,'r/m64 AND r8 (signextended).'),(71,'23 /r','AND','r16','r/m16','','Valid','Valid',0,'r16 AND r/m16.'),(72,'REX.W + 23 /r','AND','r64','r/m64','','Valid','N.E.',0,'r64 AND r/m64.'),(73,'66 0F 54 /r','ANDPD','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise logical AND of xmm2/m128 and'),(74,'0F 54 /r','ANDPS','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise logical AND of'),(75,'66 0F 55 /r','ANDNPD','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise logical AND'),(76,'0F 55 /r','ANDNPS','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise logical AND NOT of'),(77,'63 /r','ARPL','r/m16','r16','','N. E.','Valid',0,'Adjust RPL of r/m16 to not less'),(78,'62 /r','BOUND','r16','m16&16','','Invalid','Valid',0,'Check if r16 (array index) is'),(79,'62 /r','BOUND','r32','m32&32','','Invalid','Valid',0,'Check if r32 (array index) is'),(80,'0F BC /r','BSF','r16','r/m16','','Valid','Valid',0,'Bit scan forward on r/m16.'),(81,'0F BC /r','BSF','r32','r/m32','','Valid','Valid',0,'Bit scan forward on r/m32.'),(82,'0F BD /r','BSR','r16','r/m16','','Valid','Valid',0,'Bit scan reverse on r/m16.'),(83,'0F BD /r','BSR','r32','r/m32','','Valid','Valid',0,'Bit scan reverse on r/m32.'),(84,'REX.W + 0F BD','BSR','r64','r/m64','','Valid','N.E.',0,'Bit scan reverse on r/m64.'),(85,'0F C8+rd','BSWAP','r32','','','Valid','Valid',0,'Reverses the byte order of a 32-'),(86,'REX.W + 0F C8+rd','BSWAP','r64','','','Valid','N.E.',0,'Reverses the byte order of a 64-'),(87,'0F A3','BT','r/m16','r16','','Valid','Valid',0,'Store selected bit in CF'),(88,'0F A3','BT','r/m32','r32','','Valid','Valid',0,'Store selected bit in CF'),(89,'REX.W + 0F A3','BT','r/m64','r64','','Valid','N.E.',0,'Store selected bit in CF'),(90,'0F BA /4 ib','BT','r/m16','imm8','','Valid','Valid',0,'Store selected bit in CF'),(91,'0F BA /4 ib','BT','r/m32','imm8','','Valid','Valid',0,'Store selected bit in CF'),(92,'REX.W + 0F BA /4 ib','BT','r/m64','imm8','','Valid','N.E.',0,'Store selected bit in CF\r\nflag.'),(93,'0F BB','BTC','r/m16','r16','','Valid','Valid',0,'Store selected bit in CF flag\r\nand complement.'),(94,'0F BB','BTC','r/m32','r32','','Valid','Valid',0,'Store selected bit in CF flag'),(95,'REX.W + 0F BB','BTC','r/m64','r64','','Valid','N.E.',0,'Store selected bit in CF flag\r\nand complement.'),(96,'0F BA /7 ib','BTC','r/m16','imm8','','Valid','Valid',0,'Store selected bit in CF flag\r\nand complement.'),(97,'0F BA /7 ib','BTC','r/m32','imm8','','Valid','Valid',0,'Store selected bit in CF flag\r\nand complement.'),(98,'REX.W + 0F BA /7 ib','BTC','r/m64','imm8','','Valid','N.E.',0,'Store selected bit in CF flag\r\nand complement.'),(99,'0F B3','BTR','r/m16','r16','','Valid','Valid',0,'Store selected bit in CF flag\r\nand clear.'),(100,'0F B3','BTR','r/m32','r32','','Valid','Valid',0,'Store selected bit in CF flag\r\nand clear.'),(101,'REX.W + 0F B3','BTR','r/m64','r64','','Valid','N.E.',0,'Store selected bit in CF flag\r\nand clear.'),(102,'0F BA /6 ib','BTR','r/m16','imm8','','Valid','Valid',0,'Store selected bit in CF flag\r\nand clear.'),(103,'REX.W + 0F BA /6 ib','BTR','r/m64','imm8','','Valid','N.E.',0,'Store selected bit in CF flag\r\nand clear.'),(104,'0F AB','BTS','r/m16','r16','','Valid','Valid',0,'Store selected bit in CF\r\nflag and set.'),(105,'0F AB','BTS','r/m32','r32','','Valid','Valid',0,'Store selected bit in CF\r\nflag and set.'),(106,'REX.W + 0F AB','BTS','r/m64','r64','','Valid','N.E.',0,'Store selected bit in CF\r\nflag and set.'),(107,'0F BA /5 ib','BTS','r/m16','imm8','','Valid','Valid',0,'Store selected bit in CF\r\nflag and set.'),(108,'0F BA /5 ib','BTS','r/m32','imm8','','Valid','Valid',0,'Store selected bit in CF\r\nflag and set.'),(109,'REX.W + 0F BA /5 ib','BTS','r/m64','imm8','','Valid','N.E.',0,'Store selected bit in CF\r\nflag and set.'),(110,'E8 cw','CALL','rel16','','','N.S.','Valid',0,'Call near, relative, displacement relative\r\nto next instruction.'),(111,'E8 cd','CALL','rel32','','','Valid','Valid',0,'Call near, relative, displacement relative\r\nto next instruction. 32-bit\r\ndisplacement sign extended to 64-bits\r\nin 64-bit mode.'),(112,'FF /2','CALL','r/m16','','','N.E.','Valid',0,'Call near, absolute indirect, address\r\ngiven in r/m16.'),(113,'FF /2','CALL','r/m32','','','N.E.','Valid',0,'Call near, absolute indirect, address\r\ngiven in r/m32.'),(114,'FF /2','CALL','r/m64','','','Valid','N.E.',0,'Call near, absolute indirect, address\r\ngiven in r/m64.'),(115,'9A cd','CALL','ptr16:16','','','Invalid','Valid',0,'Call far, absolute, address given in\r\noperand.'),(116,'9A cp','CALL','ptr16:32','','','Invalid','Valid',0,'Call far, absolute, address given in\r\noperand.'),(117,'FF /3','CALL','m16:16','','','Valid','Valid',0,'Call far, absolute indirect address given\r\nin m16:16.\r\n\r\nIn 32-bit mode: if selector points to a\r\ngate, then RIP = 32-bit zero extended\r\ndisplacement taken from gate; else RIP\r\n= zero extended 16-bit offset from far\r\npointer referenced in the instruction.'),(118,'FF /3','CALL','m16:32','','','Valid','Valid',0,'In 64-bit mode: If selector points to a\r\ngate, then RIP = 64-bit displacement\r\ntaken from gate; else RIP = zero\r\nextended 32-bit offset from far\r\npointer referenced in the instruction.'),(119,'REX.W + FF /3','CALL','m16:64','','','Valid','N.E.',0,'In 64-bit mode: If selector points to a\r\ngate, then RIP = 64-bit displacement\r\ntaken from gate; else RIP = 64-bit\r\noffset from far pointer referenced in\r\nthe instruction.'),(120,'98','CBW','','','','Valid','Valid',0,'AX ← sign-extend of AL.'),(121,'98','CWDE','','','','Valid','Valid',0,'EAX ← sign-extend of AX.'),(122,'REX.W + 98','CDQE','','','','Valid','N.E',0,'RAX ← sign-extend of EAX.'),(123,'F8','CLC','','','','Valid','Valid',0,'Clear CF flag.'),(124,'FC','CLD','','','','Valid','Valid',0,'Clear DF flag.'),(125,'0F AE /7','CLFLUSH','m8','','','Valid','Valid',0,'Flushes cache line\r\ncontaining m8.'),(126,'FA','CLI','','','','Valid','Valid',0,'Clear interrupt flag; interrupts disabled\r\nwhen interrupt flag cleared.'),(127,'0F 06','CLTS','','','','Valid','Valid',0,'Clears TS flag in CR0.'),(128,'F5','CMC','','','','Valid','Valid',0,'Complement CF flag.'),(129,'0F 47 /r','CMOVA','r16','r/m16','','Valid','Valid',0,'Move if above (CF=0 and\r\nZF=0).'),(130,'0F 47 /r','CMOVA','r32','r/m32','','Valid','Valid',0,'Move if above (CF=0 and\r\nZF=0).'),(131,'REX.W + 0F 47 /r','CMOVA','r64','r/m64','','Valid','N.E.',0,'Move if above (CF=0 and\r\nZF=0).'),(132,'0F 43 /r','CMOVAE','r16','r/m16','','Valid','Valid',0,'Move if above or equal\r\n(CF=0).'),(133,'0F 43 /r','CMOVAE','r32','r/m32','','Valid','Valid',0,'Move if above or equal\r\n(CF=0).'),(134,'REX.W + 0F 43 /r','CMOVAE','r64','r/m64','','Valid','N.E.',0,'Move if above or equal\r\n(CF=0).'),(135,'0F 42 /r','CMOVB','r16','r/m16','','Valid','Valid',0,'Move if below (CF=1).'),(136,'0F 42 /r','CMOVB','r32','r/m32','','Valid','Valid',0,'Move if below (CF=1).'),(137,'REX.W + 0F 42 /r','CMOVB','r64','r/m64','','Valid','N.E',0,'Move if below (CF=1).'),(138,'0F 46 /r','CMOVBE','r16','r/m16','','Valid','Valid',0,'Move if below or equal\r\n(CF=1 or ZF=1).'),(139,'0F 46 /r','CMOVBE','r32','r/m32','','Valid','Valid',0,'Move if below or equal\r\n(CF=1 or ZF=1).'),(140,'REX.W + 0F 46 /r','CMOVBE','r64','r/m64','','Valid','N.E.',0,'Move if below or equal\r\n(CF=1 or ZF=1).'),(141,'0F 42 /r','CMOVC','r16','r/m16','','Valid','Valid',0,'Move if carry (CF=1).'),(142,'0F 42 /r','CMOVC','r32','r/m32','','Valid','Valid',0,'Move if carry (CF=1).'),(143,'REX.W + 0F 42 /r','CMOVC','r64','r/m64','','Valid','N.E.',0,'Move if carry (CF=1).'),(144,'0F 44 /r','CMOVE','r16','r/m16','','Valid','Valid',0,'Move if equal (ZF=1).'),(145,'0F 44 /r','CMOVE','r32','r/m32','','Valid','Valid',0,'Move if equal (ZF=1).'),(146,'REX.W + 0F 44 /r','CMOVE','r64','r/m64','','Valid','N.E.',0,'Move if equal (ZF='),(147,'0F 4F /r','CMOVG','r16','r/m16','','Valid','Valid',0,'Move if greater (ZF=0\r\nand SF=OF).'),(148,'0F 4F /r','CMOVG','r32','r/m32','','Valid','Valid',0,'Move if greater (ZF=0\r\nand SF=OF).'),(149,'REX.W + 0F 4F /r','CMOVG','r64','r/m64','','Valid','N.E.',0,'Move if greater (ZF=0\r\nand SF=OF).'),(150,'0F 4D /r','CMOVGE','r16','r/m16','','Valid','Valid',0,'Move if greater or equal\r\n(SF=OF).'),(151,'0F 4D /r','CMOVGE','r32','r/m32','','Valid','Valid',0,'Move if greater or equal\r\n(SF=OF).'),(152,'REX.W + 0F 4D /r','CMOVGE','r64','r/m64','','Valid','N.E.',0,'Move if greater or equal\r\n(SF=OF).'),(153,'0F 4C /r','CMOV','r16','r/m16','','Valid','Valid',0,'Move if less (SF≠ OF).'),(154,'0F 4C /r','CMOVL','r32','r/m32','','Valid','Valid',0,'Move if less (SF≠ OF).'),(155,'REX.W + 0F 4C /r','CMOVL','r64','r/m64','','Valid','N.E.',0,'Move if less (SF≠ OF).'),(156,'0F 4E /r','CMOVLE','r16','r/m16','','Valid','Valid',0,'Move if less or equal\r\n(ZF=1 or SF≠ OF).'),(157,'0F 4E /r','CMOVL','r32','r/m32','','Valid','Valid',0,'Move if less or equal\r\n(ZF=1 or SF≠ OF).'),(158,'REX.W + 0F 4E /r','CMOVLE','r64','r/m64','','Valid','N.E.',0,'Move if less or equal\r\n(ZF=1 or SF≠ OF).'),(159,'0F 46 /r','CMOVNA','r16','r/m16','','Valid','Valid',0,'Move if not above (CF=1\r\nor ZF=1).'),(160,'0F 46 /','CMOVNA','r32','r/m32','','Valid','Valid',0,'Move if not above (CF=1\r\nor ZF=1).'),(161,'REX.W + 0F 46 /r','CMOVNA','r64','r/m64','','Valid','N.E.',0,'Move if not above (CF=1\r\nor ZF=1).'),(162,'0F 42 /r','CMOVNAE','r16','r/m16','','Valid','Valid',0,'Move if not above or\r\nequal (CF=1).'),(163,'0F 42 /r','CMOVNAE','r32','r/m32','','Valid','Valid',0,'Move if not above or\r\nequal (CF=1).'),(164,'REX.W + 0F 42 /r','CMOVNAE','r64','r/m64','','Valid','N.E.',0,'Move if not above or\r\nequal (CF=1).'),(165,'0F 43 /r','CMOVNB','r16','r/m16','','Valid','Valid',0,'Move if not below\r\n(CF=0).'),(166,'0F 43 /r','CMOVNB','r32','r/m32','','Valid','Valid',0,'Move if not below\r\n(CF=0).'),(167,'REX.W + 0F 43 /r','CMOVNB','r64','r/m64','','Valid','N.E.',0,'Move if not below\r\n(CF=0).'),(168,'0F 47 /r','CMOVNBE','r16','r/m16','','Valid','Valid',0,'Move if not below or\r\nequal (CF=0 and ZF=0).'),(169,'0F 47 /r','CMOVNBE','r32','r/m32','','Valid','Valid',0,'Move if not below or\r\nequal (CF=0 and ZF=0).'),(170,'REX.W + 0F 47 /r','CMOVNBE','r64','r/m64','','Valid','N.E.',0,'Move if not below or\r\nequal (CF=0 and ZF=0).'),(171,'0F 43 /r','CMOVNC','r16','r/m16','','Valid','Valid',0,'Move if not carry (CF=0).'),(172,'0F 43 /r','CMOVNC','r32','r/m32','','Valid','Valid',0,'Move if not carry (CF=0).'),(173,'REX.W + 0F 43 /r','CMOVNC','r64','r/m64','','Valid','N.E.',0,'Move if not carry (CF=0).'),(174,'0F 45 /r','CMOVNE','r16','r/m16','','Valid','Valid',0,'Move if not equal (ZF=0).'),(175,'0F 45 /r','CMOVNE','r32','r/m32','','Valid','Valid',0,'Move if not equal (ZF=0).'),(176,'REX.W + 0F 45 /r','CMOVNE','r64','r/m64','','Valid','N.E.',0,'Move if not equal (ZF=0).'),(177,'0F 4E /r','CMOVNG','r16','r/m16','','Valid','Valid',0,'Move if not greater\r\n(ZF=1 or SF≠ OF).'),(178,'0F 4E /r','CMOVNG','r32','r/m32','','Valid','Valid',0,'Move if not greater\r\n(ZF=1 or SF≠ OF).'),(179,'REX.W + 0F 4E /r','CMOVNG','r64','r/m64','','Valid','N.E.',0,'Move if not greater\r\n(ZF=1 or SF≠ OF).'),(180,'0F 4C /r','CMOVNGE','r16','r/m16','','Valid','Valid',0,'Move if not greater or\r\nequal (SF≠ OF).'),(181,'0F 4C /r','CMOVNGE','r32','r/m32','','Valid','Valid',0,'Move if not greater or\r\nequal (SF≠ OF).'),(182,'REX.W + 0F 4C /r','CMOVNGE','r64','r/m64','','Valid','N.E.',0,'Move if not greater or\r\nequal (SF≠ OF).'),(183,'0F 4D /r','CMOVNL','r16','r/m16','','Valid','Valid',0,'Move if not less (SF=OF).'),(184,'0F 4D /r','CMOVNL','r32','r/m32','','Valid','Valid',0,'Move if not less (SF=OF).'),(185,'REX.W + 0F 4D /r','CMOVNL','r64','r/m64','','Valid','N.E.',0,'Move if not less (SF=OF).'),(186,'0F 4F /r','CMOVNLE','r16','r/m16','','Valid','Valid',0,'Move if not less or equal\r\n(ZF=0 and SF=OF).'),(187,'0F 4F /r','CMOVNLE','r32','r/m32','','Valid','Valid',0,'Move if not less or equal\r\n(ZF=0 and SF=OF).'),(188,'REX.W + 0F 4F /r','CMOVNLE','r64','r/m64','','Valid','N.E.',0,'Move if not less or equal\r\n(ZF=0 and SF=OF).'),(189,'0F 41 /r','CMOVNO','r16','r/m16','','Valid','Valid',0,'Move if not overflow\r\n(OF=0).'),(190,'0F 41 /r','CMOVNO','r32','r/m32','','Valid','Valid',0,'Move if not overflow\r\n(OF=0).'),(191,'REX.W + 0F 41 /r','CMOVNO','r64','r/m64','','Valid','N.E.',0,'Move if not overflow\r\n(OF=0).'),(192,'0F 4B /r','CMOVNP','r16','r/m16','','Valid','Valid',0,'Move if not parity\r\n(PF=0).'),(193,'0F 4B /r','CMOVNP','r32','r/m32','','Valid','Valid',0,'Move if not parity\r\n(PF=0).'),(194,'REX.W + 0F 4B /r','CMOVNP','r64','r/m64','','Valid','N.E.',0,'Move if not parity\r\n(PF=0).'),(195,'0F 49 /r','CMOVNS','r16','r/m16','','Valid','Valid',0,'Move if not sign (SF=0).'),(196,'0F 49 /r','CMOVNS','r32','r/m32','','Valid','Valid',0,'Move if not sign (SF=0).Move if not sign (SF=0).'),(197,'REX.W + 0F 49 /r','CMOVNS','r64','r/m64','','Valid','N.E.',0,'Move if not sign (SF=0).'),(198,'0F 45 /r','CMOVNZ','r16','r/m16','','Valid','Valid',0,'Move if not zero (ZF=0).'),(199,'0F 45 /r','CMOVNZ','r32','r/m32','','Valid','Valid',0,'Move if not zero (ZF=0).'),(200,'REX.W + 0F 45 /r','CMOVNZ','r64','r/m64','','Valid','N.E.',0,'Move if not zero (ZF=0).'),(201,'0F 40 /r','CMOVO','r16','r/m16','','Valid','Valid',0,'Move if overflow (OF=0).'),(202,'0F 40 /r','CMOVO','r32','r/m32','','Valid','Valid',0,'Move if overflow (OF=0).'),(203,'REX.W + 0F 40 /r','CMOVO','r64','r/m64','','Valid','N.E.',0,'Move if overflow (OF=0).'),(204,'0F 4A /r','CMOVP','r16','r/m16','','Valid','Valid',0,'Move if parity (PF=1).'),(205,'0F 4A /r','CMOVP','r32','r/m32','','Valid','Valid',0,'Move if parity (PF=1).'),(206,'REX.W + 0F 4A /r','CMOVP','r64','r/m64','','Valid','N.E.',0,'Move if parity (PF=1).'),(207,'0F 4A /r','CMOVPE','r16','r/m16','','Valid','Valid',0,'Move if parity even\r\n(PF=1).'),(208,'0F 4A /r','CMOVPE','r32','r/m32','','Valid','Valid',0,'Move if parity even\r\n(PF=1).'),(209,'REX.W + 0F 4A /r','CMOVPE','r64','r/m64','','Valid','N.E.',0,'Move if parity even\r\n(PF=1).'),(210,'0F 4B /r','CMOVPO','r16','r/m16','','Valid','Valid',0,'Move if parity odd\r\n(PF=0).'),(211,'0F 4B /r','CMOVPO','r32','r/m32','','Valid','Valid',0,'Move if parity odd\r\n(PF=0).'),(212,'REX.W + 0F 4B /r','CMOVPO','r64','r/m64','','Valid','N.E.',0,'Move if parity odd\r\n(PF=0).'),(213,'0F 48 /r','CMOVS','r16','r/m16','','Valid','Valid',0,'Move if sign (SF=1).'),(214,'0F 48 /r','CMOVS','r32','r/m32','','Valid','Valid',0,'Move if sign (SF=1).'),(215,'REX.W + 0F 48 /r','CMOVS','r64','r/m64','','Valid','N.E.',0,'Move if sign (SF=1).'),(216,'0F 44 /r','CMOVZ','r16','r/m16','','Valid','Valid',0,'Move if zero (ZF=1).'),(217,'0F 44 /r','CMOVZ','r32','r/m32','','Valid','Valid',0,'Move if zero (ZF=1).'),(218,'REX.W + 0F 44 /r','CMOVZ','r64','r/m64','','Valid','N.E.',0,'Move if zero (ZF=1).'),(219,'66 0F C2 /r ib','CMPPD','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Compare packed doubleprecision\r\nfloating-point\r\nvalues in xmm2/m128 and\r\nxmm1 using imm8 as\r\ncomparison predicate.'),(220,'0F C2 /r ib','CMPPS','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Compare packed singleprecision\r\nfloating-point values\r\nin xmm2/mem and xmm1\r\nusing imm8 as comparison\r\npredicate.'),(221,'A6','CMPS','m8','m8','','Valid','Valid',0,'For legacy mode, compare byte at\r\naddress DS:(E)SI with byte at\r\naddress ES:(E)DI; For 64-bit mode\r\ncompare byte at address (R|E)SI to\r\nbyte at address (R|E)DI. The status\r\nflags are set accordingly.'),(222,'A7','CMPS','m16','m16','','Valid','Valid',0,'For legacy mode, compare word at\r\naddress DS:(E)SI with word at\r\naddress ES:(E)DI; For 64-bit mode\r\ncompare word at address (R|E)SI\r\nwith word at address (R|E)DI. The\r\nstatus flags are set accordingly.'),(223,'A7','CMPS','m32','m32','','Valid','Valid',0,'For legacy mode, compare dword\r\nat address DS:(E)SI at dword at\r\naddress ES:(E)DI; For 64-bit mode\r\ncompare dword at address (R|E)SI\r\nat dword at address (R|E)DI. The\r\nstatus flags are set accordingly.'),(224,'REX.W + A7','CMPS','m64','m64','','Valid','N.E.',0,'Compares quadword at address\r\n(R|E)SI with quadword at address\r\n(R|E)DI and sets the status flags\r\naccordingly.'),(225,'A6','CMPSB','','','','Valid','Valid',0,'For legacy mode, compare byte at\r\naddress DS:(E)SI with byte at\r\naddress ES:(E)DI; For 64-bit mode\r\ncompare byte at address (R|E)SI\r\nwith byte at address (R|E)DI. The\r\nstatus flags are set accordingly.'),(226,'A7','CMPSW','','','','Valid','Valid',0,'For legacy mode, compare word at\r\naddress DS:(E)SI with word at\r\naddress ES:(E)DI; For 64-bit mode\r\ncompare word at address (R|E)SI\r\nwith word at address (R|E)DI. The\r\nstatus flags are set accordingly.'),(227,'A7','CMPSD','','','','Valid','Valid',0,'For legacy mode, compare dword\r\nat address DS:(E)SI with dword at\r\naddress ES:(E)DI; For 64-bit mode\r\ncompare dword at address (R|E)SI\r\nwith dword at address (R|E)DI. The\r\nstatus flags are set accordingly.'),(228,'REX.W + A7','CMPSQ','','','','Valid','N.E.',0,'Compares quadword at address\r\n(R|E)SI with quadword at address\r\n(R|E)DI and sets the status flags\r\naccordingly.'),(229,'F2 0F C2 /r ib','CMPSD','xmm1','xmm2/m64','imm8','Valid','Valid',0,'Compare low doubleprecision\r\nfloating-point\r\nvalue in xmm2/m64 and\r\nxmm1 using imm8 as\r\ncomparison predicate.'),(230,'F3 0F C2 /r ib','CMPSS','xmm1','xmm2/m32','imm8','Valid','Valid',0,'Compare low single-precision\r\nfloating-point value in\r\nxmm2/m32 and xmm1 using\r\nimm8 as comparison\r\npredicate.'),(231,'0F B0/r','CMPXCHG','r/m8','r8','','Valid','Valid',0,'Compare AL with r/m8. If\r\nequal, ZF is set and r8 is\r\nloaded into r/m8. Else, clear\r\nZF and load r/m8 into AL.'),(232,'REX + 0F B0/r','CMPXCHG','r/m8','r8','','Valid','N.E.',0,'Compare AL with r/m8. If\r\nequal, ZF is set and r8 is\r\nloaded into r/m8. Else, clear\r\nZF and load r/m8 into AL.'),(233,'0F B1/r','CMPXCHG','r/m16','r16','','Valid','Valid',0,'Compare AX with r/m16. If\r\nequal, ZF is set and r16 is\r\nloaded into r/m16. Else,\r\nclear ZF and load r/m16\r\ninto AX.'),(234,'0F B1/r','CMPXCHG','r/m32','r32','','Valid','Valid',0,'Compare EAX with r/m32.\r\nIf equal, ZF is set and r32 is\r\nloaded into r/m32. Else,\r\nclear ZF and load r/m32\r\ninto EAX.'),(235,'REX.W + 0F B1/r','CMPXCHG','r/m64','r64','','Valid','N.E.',0,'Compare RAX with r/m64.\r\nIf equal, ZF is set and r64 is\r\nloaded into r/m64. Else,\r\nclear ZF and load r/m64\r\ninto RAX.'),(236,'0F C7 /1 m64','CMPXCHG8B','m64','','','Valid','Valid',0,'Compare EDX:EAX with\r\nm64. If equal, set ZF and\r\nload ECX:EBX into m64.\r\nElse, clear ZF and load m64\r\ninto EDX:EAX.'),(237,'REX.W + 0F C7 /1 m128','CMPXCHG16B','m128','','','Valid','N.E.',0,'Compare RDX:RAX with\r\nm128. If equal, set ZF and\r\nload RCX:RBX into m128.\r\nElse, clear ZF and load\r\nm128 into RDX:RAX.'),(238,'66 0F 2F /r','COMISD','xmm1','xmm2/m64','','Valid','Valid',0,'Compare low double-precision\r\nfloating-point values in xmm1\r\nand xmm2/mem64 and set\r\nthe EFLAGS flags accordingly.'),(239,'0F 2F /r','COMISS','xmm1','xmm2/m32','','Valid','Valid',0,'Compare low single-precision\r\nfloating-point values in xmm1 and\r\nxmm2/mem32 and set the EFLAGS\r\nflags accordingly.'),(240,'0F A2','CPUID','','','','Valid','Valid',0,'Returns processor identification\r\nand feature information to the\r\nEAX, EBX, ECX, and EDX registers,\r\nas determined by input entered in\r\nEAX (in some cases, ECX as well).'),(241,'F3 0F E6','CVTDQ2PD','xmm1','xmm2/m64','','Valid','Valid',0,'Convert two packed signed\r\ndoubleword integers from\r\nxmm2/m128 to two packed\r\ndouble-precision floating-point\r\nvalues in xmm1.'),(242,'0F 5B /r','CVTDQ2PS','xmm1','xmm2/m128','','Valid','Valid',0,'Convert four packed signed\r\ndoubleword integers from\r\nxmm2/m128 to four packed\r\nsingle-precision floating-point\r\nvalues in xmm1.'),(243,'F2 0F E6','CVTPD2DQ','xmm1','xmm2/m128','','Valid','Valid',0,'Convert two packed doubleprecision\r\nfloating-point values\r\nfrom xmm2/m128 to two\r\npacked signed doubleword\r\nintegers in xmm1.'),(244,'66 0F 2D /r','CVTPD2PI','mm','xmm/m128','','Valid','Valid',0,'Convert two packed doubleprecision\r\nfloating-point\r\nvalues from xmm/m128 to\r\ntwo packed signed\r\ndoubleword integers in mm.'),(245,'66 0F 5A /r','CVTPD2PS','xmm1','xmm2/m128','','Valid','Valid',0,'Convert two packed doubleprecision\r\nfloating-point values in\r\nxmm2/m128 to two packed singleprecision\r\nfloating-point values in\r\nxmm1.'),(246,'66 0F 2A /r','CVTPI2PD','xmm','mm/m64','','Valid','Valid',0,'Convert two packed signed\r\ndoubleword integers from\r\nmm/mem64 to two packed doubleprecision\r\nfloating-point values in\r\nxmm.'),(247,'0F 2A /r','CVTPI2PS','xmm','mm/m64','','Valid','Valid',0,'Convert two signed doubleword\r\nintegers from mm/m64 to two singleprecision\r\nfloating-point values in xmm.'),(248,'66 0F 5B /r','CVTPS2DQ','xmm1','xmm2/m128','','Valid','Valid',0,'Convert four packed single-precision\r\nfloating-point values from\r\nxmm2/m128 to four packed signed\r\ndoubleword integers in xmm1.'),(249,'0F 5A /r','CVTPS2PD','xmm1','xmm2/m64','','Valid','Valid',0,'Convert two packed single-precision\r\nfloating-point values in xmm2/m64\r\nto two packed double-precision\r\nfloating-point values in xmm1.'),(250,'0F 2D /r','CVTPS2PI','mm','xmm/m64','','Valid','Valid',0,'Convert two packed single-precision\r\nfloating-point values from xmm/m64 to\r\ntwo packed signed doubleword integers in\r\nmm.'),(251,'F2 0F 2D /r','CVTSD2SI','r32','xmm/m64','','Valid','Valid',0,'Convert one double-precision'),(252,'F2 REX.W 0F 2D /r','CVTSD2SI','r64','xmm/m64','','Valid','N.E.',0,'Convert one double-precision\r\nfloating-point value from\r\nxmm/m64 to one signed\r\nquadword integer signextended\r\ninto r64.'),(253,'F2 0F 5A /r','CVTSD2SS','xmm1','xmm2/m64','','Valid','Valid',0,'Convert one double-precision floatingpoint\r\nvalue in xmm2/m64 to one\r\nsingle-precision floating-point value in\r\nxmm1.'),(254,'F2 0F 2A /r','CVTSI2S','xmm','r/m32','','Valid','Valid',0,'Convert one signed doubleword\r\ninteger from r/m32 to one\r\ndouble-precision floating-point\r\nvalue in xmm.'),(255,'F2 REX.W 0F 2A /r','CVTSI2SD','xmm','r/m64','','Valid','N.E.',0,'Convert one signed quadword\r\ninteger from r/m64 to one\r\ndouble-precision floating-point\r\nvalue in xmm.'),(256,'F3 0F 2A /r','CVTSI2SS','xmm','r/m32','','Valid','Valid',0,'Convert one signed doubleword\r\ninteger from r/m32 to one singleprecision\r\nfloating-point value in\r\nxmm.'),(257,'F3 REX.W 0F 2A /r','CVTSI2SS','xmm','r/m64','','Valid','N.E.',0,'Convert one signed quadword\r\ninteger from r/m64 to one singleprecision\r\nfloating-point value in\r\nxmm.'),(258,'F3 0F 5A /r','CVTSS2SD','xmm1','xmm2/m32','','Valid','Valid',0,'Convert one single-precision floatingpoint\r\nvalue in xmm2/m32 to one\r\ndouble-precision floating-point value\r\nin xmm1.'),(259,'F3 0F 2D /r','CVTSS2SI','r32','xmm/m32','','Valid','Valid',0,'Convert one single-precision\r\nfloating-point value from\r\nxmm/m32 to one signed\r\ndoubleword integer in r32.'),(260,'F3 REX.W 0F 2D /r','CVTSS2SI','r64','xmm/m32','','Valid','N.E.',0,'Convert one single-precision\r\nfloating-point value from\r\nxmm/m32 to one signed\r\nquadword integer in r64.'),(261,'66 0F 2C /r','CVTTPD2PI','mm','xmm/m128','','Valid','Valid',0,'Convert two packer double-precision\r\nfloating-point values from xmm/m128\r\nto two packed signed doubleword\r\nintegers in mm using truncation.'),(262,'66 0F E6','CVTTPD2DQ','xmm1','xmm2/m128','','Valid','Valid',0,'Convert two packed doubleprecision\r\nfloating-point values\r\nfrom xmm2/m128 to two packed\r\nsigned doubleword integers in\r\nxmm1 using truncation.'),(263,'F3 0F 5B /r','VTTPS2DQ','xmm1','xmm2/m128','','Valid','Valid',0,'Convert four single-precision\r\nfloating-point values from\r\nxmm2/m128 to four signed\r\ndoubleword integers in xmm1 using\r\ntruncation.'),(264,'0F 2C /r','CVTTPS2PI','mm','xmm/m64','','Valid','Valid',0,'Convert two single-precision floatingpoint\r\nvalues from xmm/m64 to two\r\nsigned doubleword signed integers in mm\r\nusing truncation.'),(265,'F2 0F 2C /r','CVTTSD2SI','r32','xmm/m64','','Valid','Valid',0,'Convert one double-precision\r\nfloating-point value from\r\nxmm/m64 to one signed\r\ndoubleword integer in r32 using\r\ntruncation.'),(266,'F2 REX.W 0F 2C /r','CVTTSD2SI','r64','xmm/m64','','Valid','N.E.',0,'Convert one double precision\r\nfloating-point value from\r\nxmm/m64 to one\r\nsignedquadword integer in r64\r\nusing truncation.'),(267,'F3 0F 2C /r','CVTTSS2SI','r32','xmm/m32','','Valid','Valid',0,'Convert one single-precision\r\nfloating-point value from\r\nxmm/m32 to one signed\r\ndoubleword integer in r32\r\nusing truncation.'),(268,'F3 REX.W 0F 2C /r','CVTTSS2SI','r64','xmm/m32','','Valid','N.E.',0,'Convert one single-precision\r\nfloating-point value from\r\nxmm/m32 to one signed\r\nquadword integer in r64 using\r\ntruncation.'),(269,'99','CWD','','','','Valid','Valid',0,'DX:AX ← sign-extend of AX.'),(270,'99','CDQ','','','','Valid','Valid',0,'EDX:EAX ← sign-extend of EAX.'),(271,'REX.W + 99','CQO','','','','Valid','N.E.',0,'RDX:RAX← sign-extend of RAX.'),(272,'27','DAA','','','','Invalid','Invalid',0,'Decimal adjust AL after addition.'),(273,'2F','DAS','','','','Invalid','Invalid',0,'Decimal adjust AL after\r\nsubtraction.'),(274,'FE /1','DEC','r/m8','','','Valid','Valid',0,'Decrement r/m8 by 1.'),(275,'REX + FE /1','DEC','r/m8','','','Valid','N.E.',0,'Decrement r/m8 by 1.'),(276,'FF /1','DEC','r/m16','','','Valid','Valid',0,'Decrement r/m16 by 1.'),(277,'FF /1','DEC','r/m32','','','Valid','Valid',0,'Decrement r/m32 by 1.'),(278,'REX.W + FF /1','DEC','r/m64','','','Valid','N.E.',0,'Decrement r/m64 by 1.'),(279,'48+rw','DEC','r16','','','N.E.','Valid',0,'Decrement r16 by 1.'),(280,'48+rd','DEC','r32','','','N.E.','Valid',0,'Decrement r32 by 1.'),(281,'F6 /6','DIV','r/m8','','','Valid','Valid',0,'Unsigned divide AX by r/m8, with\r\nresult stored in AL ← Quotient, AH ←\r\nRemainder.'),(282,'REX + F6 /6','DIV','r/m8','','','Valid','N.E.',0,'Unsigned divide DX:AX by r/m16, with\r\nresult stored in AX ← Quotient, DX ←\r\nRemainder.'),(283,'F7 /6','DIV','r/m32','','','Valid','Valid',0,'Unsigned divide EDX:EAX by r/m32,\r\nwith result stored in EAX ← Quotient,\r\nEDX ← Remainder.'),(284,'REX.W + F7 /6','DIV','r/m64','','','Valid','N.E.',0,'Unsigned divide RDX:RAX by r/m64,\r\nwith result stored in RAX ← Quotient,\r\nRDX ← Remainder.'),(285,'66 0F 5E /r','DIVPD','xmm1','xmm2/m128','','Valid','Valid',0,'Divide packed double-precision floatingpoint\r\nvalues in xmm1 by packed doubleprecision\r\nfloating-point values\r\nxmm2/m128.'),(286,'0F 5E /r','DIVPS','xmm1','xmm2/m128','','Valid','Valid',0,'Divide packed single-precision floatingpoint\r\nvalues in xmm1 by packed singleprecision\r\nfloating-point values\r\nxmm2/m128.'),(287,'F2 0F 5E /r','DIVSD','xmm1','xmm2/m64','','Valid','Valid',0,'Divide low double-precision floatingpoint\r\nvalue n xmm1 by low doubleprecision\r\nfloating-point value in\r\nxmm2/mem64.'),(288,'F3 0F 5E /r','DIVSS','xmm1','xmm2/m32','','Valid','Valid',0,'Divide low single-precision floatingpoint\r\nvalue in xmm1 by low singleprecision\r\nfloating-point value in\r\nxmm2/m32.'),(289,'0F 77','EMMS','','','','Valid','Valid',0,'Set the x87 FPU tag word to empty.'),(290,'C8 iw 00','ENTER','imm16','','','Valid','Valid',0,'Create a stack frame for a\r\nprocedure.'),(291,'C8 iw 01','ENTER','imm16','1','','Valid','Valid',0,'Create a nested stack frame for a\r\nprocedure.'),(292,'C8 iw ib','ENTER','imm16','imm8','','Valid','Valid',0,'Create a nested stack frame for a\r\nprocedure.'),(293,'D9 F0','F2XM1','','','','Valid','Valid',0,'Replace ST(0) with (2ST(0) – 1).'),(294,'D9 E1','FABS','','','','Valid','Valid',0,'Replace ST with its absolute value.'),(295,'D8 /0','FADD','m32fp','','','Valid','Valid',0,'Add m32fp to ST(0) and store result\r\nin ST(0).'),(296,'DC /0','FADD','m64fp','','','Valid','Valid',0,'Add m64fp to ST(0) and store result\r\nin ST(0).'),(297,'D8 C0+i','FADD','ST(0)','ST(i)','','Valid','Valid',0,'Add ST(0) to ST(i) and store result in\r\nST(0).'),(298,'DC C0+i','FADD','ST(i)','ST(0)','','Valid','Valid',0,'Add ST(i) to ST(0) and store result in\r\nST(i).'),(299,'DE C0+i','FADDP','ST(i)','ST(0)','','Valid','Valid',0,'Add ST(0) to ST(i), store result in\r\nST(i), and pop the register stack.'),(300,'DE C1','FADDP','','','','Valid','Valid',0,'Add ST(0) to ST(1), store result in\r\nST(1), and pop the register stack.'),(301,'DA /0','FIADD','m32int','','','Valid','Valid',0,'Add m32int to ST(0) and store\r\nresult in ST(0).'),(302,'DE /0','FIADD','m16int','','','Valid','Valid',0,'Add m16int to ST(0) and store\r\nresult in ST(0).'),(303,'DF /4','FBLD','m80','dec','','Valid','Valid',0,'Convert BCD value to floating-point and\r\npush onto the FPU stack.'),(304,'DF /6','FBSTP','m80bcd','','','Valid','Valid',0,'Store ST(0) in m80bcd and pop ST(0).'),(305,'D9 E0','FCHS','','','','Valid','Valid',0,'Complements sign of ST(0).'),(306,'9B DB E2','FCLEX','','','','Valid','Valid',0,'Clear floating-point exception flags after\r\nchecking for pending unmasked floatingpoint\r\nexceptions.'),(307,'DB E2','FNCLEX','','','','Valid','Valid',0,'Clear floating-point exception flags\r\nwithout checking for pending unmasked\r\nfloating-point exceptions.'),(308,'DA C0+i','FCMOVB','ST(0)','ST(i)','','Valid','Valid',0,'Move if below (CF=1).'),(309,'DA C8+i','FCMOVE','ST(0)','ST(i)','','Valid','Valid',0,'Move if equal (ZF=1).'),(310,'DA D0+i','FCMOVBE','ST(0)','ST(i)','','Valid','Valid',0,'Move if below or equal (CF=1 or\r\nZF=1).'),(311,'DA D8+i','FCMOVU','ST(0)','ST(i)','','Valid','Valid',0,'Move if unordered (PF=1).'),(312,'DB C0+i','FCMOVNB','ST(0)','ST(i)','','Valid','Valid',0,'Move if not below (CF=0).'),(313,'DB C8+i','FCMOVNE','ST(0)','ST(i)','','Valid','Valid',0,'Move if not equal (ZF=0).'),(314,'DB D0+i','FCMOVNBE','ST(0)','ST(i)','','Valid','Valid',0,'Move if not below or equal (CF=0\r\nand ZF=0).'),(315,'DB D8+i','FCMOVNU','ST(0)','ST(i)','','Valid','Valid',0,'Move if not unordered (PF=0).'),(316,'D8 /2','FCOM','m32fp','','','Valid','Valid',0,'Compare ST(0) with m32fp.'),(317,'DC /2','FCOM','m64fp','','','Valid','Valid',0,'Compare ST(0) with m64fp.'),(318,'D8 D0+i','FCOM','ST(i)','','','Valid','Valid',0,'Compare ST(0) with ST(i).'),(319,'D8 D1','FCOM','','','','Valid','Valid',0,'Compare ST(0) with ST(1).'),(320,'D8 /3','FCOMP','m32fp','','','Valid','Valid',0,'Compare ST(0) with m32fp and\r\npop register stack.'),(321,'DC /3','FCOMP','m64fp','','','Valid','Valid',0,'Compare ST(0) with m64fp and\r\npop register stack.'),(322,'D8 D8+i','FCOMP','ST(i)','','','Valid','Valid',0,'Compare ST(0) with ST(i) and pop\r\nregister stack.'),(323,'D8 D9','FCOMP','','','','Valid','Valid',0,'Compare ST(0) with ST(1) and pop\r\nregister stack.'),(324,'DE D9','FCOMPP','','','','Valid','Valid',0,'Compare ST(0) with ST(1) and pop\r\nregister stack twice.'),(325,'DB F0+i','FCOMI','ST','ST(i)','','Valid','Valid',0,'Compare ST(0) with ST(i) and set status\r\nflags accordingly.'),(326,'DF F0+i','FCOMIP','ST','ST(i)','','Valid','Valid',0,'Compare ST(0) with ST(i), set status flags\r\naccordingly, and pop register stack.'),(327,'DB E8+i','FUCOMI','ST','ST(i)','','Valid','Valid',0,'Compare ST(0) with ST(i), check for\r\nordered values, and set status flags\r\naccordingly.'),(328,'DF E8+i','FUCOMIP','ST','ST(i)','','Valid','Valid',0,'Compare ST(0) with ST(i), check for\r\nordered values, set status flags\r\naccordingly, and pop register stack.'),(329,'D9 FF','FCOS','','','','Valid','Valid',0,'Replace ST(0) with its cosine.'),(330,'D9 F6','FDECSTP','','','','Valid','Valid',0,'Decrement TOP field in FPU status\r\nword.'),(331,'D8 /6','FDIV','m32fp','','','Valid','Valid',0,'Divide ST(0) by m32fp and store\r\nresult in ST(0).'),(332,'DC /6','FDIV','m64fp','','','Valid','Valid',0,'Divide ST(0) by m64fp and store\r\nresult in ST(0).'),(333,'D8 F0+i','FDIV','ST(0)','ST(i)','','Valid','Valid',0,'Divide ST(0) by ST(i) and store result\r\nin ST(0).'),(334,'DC F8+i','FDIV','ST(i)','ST(0)','','Valid','Valid',0,'Divide ST(i) by ST(0) and store result\r\nin ST(i).'),(335,'DE F8+i','FDIVP','ST(i)','ST(0)','','Valid','Valid',0,'Divide ST(i) by ST(0), store result in\r\nST(i), and pop the register stack.'),(336,'DE F9','FDIVP','','','','Valid','Valid',0,'Divide ST(1) by ST(0), store result in\r\nST(1), and pop the register stack.'),(337,'DA /6','FIDIV','m32int','','','Valid','Valid',0,'Divide ST(0) by m32int and store\r\nresult in ST(0).'),(338,'DE /6','FIDIV','m16int','','','Valid','Valid',0,'Divide ST(0) by m64int and store\r\nresult in ST(0).'),(339,'D8 /7','FDIVR','m32fp','','','Valid','Valid',0,'Divide m32fp by ST(0) and store result\r\nin ST(0).'),(340,'DC /7','FDIVR','m64fp','','','Valid','Valid',0,'Divide m64fp by ST(0) and store result\r\nin ST(0).'),(341,'D8 F8+i','FDIVR','ST(0)','ST(i)','','Valid','Valid',0,'Divide ST(i) by ST(0) and store result in\r\nST(0).'),(342,'DC F0+i','FDIVR','ST(i)','ST(0)','','Valid','Valid',0,'Divide ST(0) by ST(i) and store result in\r\nST(i).'),(343,'DE F0+i','FDIVRP','ST(i)','ST(0)','','Valid','Valid',0,'Divide ST(0) by ST(i), store result in\r\nST(i), and pop the register stack.'),(344,'DE F1','FDIVRP','','','','Valid','Valid',0,'Divide ST(0) by ST(1), store result in\r\nST(1), and pop the register stack.'),(345,'DA /7','FIDIVR','m32int','','','Valid','Valid',0,'Divide m32int by ST(0) and store result\r\nin ST(0).'),(346,'DE /7','FIDIVR','m16int','','','Valid','Valid',0,'Divide m16int by ST(0) and store result\r\nin ST(0).'),(347,'DD C0+i','FFREE','ST(i)','','','Valid','Valid',0,'Sets tag for ST(i) to empty.'),(348,'DE /2','FICOM','m16int','','','Valid','Valid',0,'Compare ST(0) with m16int.'),(349,'DA /2','FICOM','m32int','','','Valid','Valid',0,'Compare ST(0) with m32int.'),(350,'DE /3','FICOMP','m16int','','','Valid','Valid',0,'Compare ST(0) with m16int and pop\r\nstack register.'),(351,'DA /3','FICOMP','m32int','','','Valid','Valid',0,'Compare ST(0) with m32int and pop\r\nstack register.'),(352,'DF /0','FILD','m16int','','','Valid','Valid',0,'Push m16int onto the FPU register\r\nstack.'),(353,'DB /0','FILD','m32int','','','Valid','Valid',0,'Push m32int onto the FPU register\r\nstack.'),(354,'DF /5','FILD','m64int','','','Valid','Valid',0,'Push m64int onto the FPU register\r\nstack.'),(355,'D9 F7','FINCSTP','','','','Valid','Valid',0,'Increment the TOP field in the FPU\r\nstatus register.'),(356,'9B DB E3','FINIT','','','','Valid','Valid',0,'Initialize FPU after checking for pending\r\nunmasked floating-point exceptions.'),(357,'DB E3','FNINIT','','','','Valid','Valid',0,'Initialize FPU without checking for\r\npending unmasked floating-point\r\nexceptions.'),(358,'DF /2','FIST','m16int','','','Valid','Valid',0,'Store ST(0) in m16int.'),(359,'DB /2','FIST','m32int','','','Valid','Valid',0,'Store ST(0) in m32int.'),(360,'DF /3','FISTP','m16int','','','Valid','Valid',0,'Store ST(0) in m16int and pop\r\nregister stack.'),(361,'DB /3','FISTP','m32int','','','Valid','Valid',0,'Store ST(0) in m32int and pop\r\nregister stack.'),(362,'DF /7','FISTP','m64int','','','Valid','Valid',0,'Store ST(0) in m64int and pop\r\nregister stack.'),(363,'DF /1','FISTTP','m16int','','','Valid','Valid',0,'Store ST(0) in m16int with\r\ntruncation.'),(364,'DB /1','FISTTP','m32int','','','Valid','Valid',0,'Store ST(0) in m32int with\r\ntruncation.'),(365,'DD /1','FISTTP','m64int','','','Valid','Valid',0,'Store ST(0) in m64int with\r\ntruncation.'),(366,'D9 /0','FLD','m32fp','','','Valid','Valid',0,'Push m32fp onto the FPU register stack.'),(367,'DD /0','FLD','m64fp','','','Valid','Valid',0,'Push m64fp onto the FPU register stack.'),(368,'DB /5','FLD','m80fp','','','Valid','Valid',0,'Push m80fp onto the FPU register stack.'),(369,'D9 C0+i','FLD','ST(i)','','','Valid','Valid',0,'Push ST(i) onto the FPU register stack.'),(370,'D9 E8','FLD1','','','','Valid','Valid',0,'Push +1.0 onto the FPU register stack.'),(371,'D9 E9','FLDL2T','','','','Valid','Valid',0,'Push log210 onto the FPU register stack.'),(372,'D9 EA','FLDL2E','','','','Valid','Valid',0,'Push log2e onto the FPU register stack.'),(373,'D9 EB','FLDPI','','','','Valid','Valid',0,'Push pi onto the FPU register stack.'),(374,'D9 EC','FLDLG2','','','','Valid','Valid',0,'Push log102 onto the FPU register stack.'),(375,'D9 ED','FLDLN2','','','','Valid','Valid',0,'Push loge2 onto the FPU register stack.'),(376,'D9 EE','FLDZ','','','','Valid','Valid',0,'Push +0.0 onto the FPU register stack.'),(377,'D9 /5','FLDCW','m2byte','','','Valid','Valid',0,'Load FPU control word from m2byte.'),(378,'D9 /4','FLDENV','m14/28byte','','','Valid','Valid',0,'Load FPU environment from\r\nm14byte or m28byte.'),(379,'D8 /1','FMUL','m32fp','','','Valid','Valid',0,'Multiply ST(0) by m32fp and store\r\nresult in ST(0).'),(380,'DC /1','FMUL','m64fp','','','Valid','Valid',0,'Multiply ST(0) by m64fp and store\r\nresult in ST(0).'),(381,'D8 C8+i','FMUL','ST(0)','ST(i)','','Valid','Valid',0,'Multiply ST(0) by ST(i) and store result\r\nin ST(0).'),(382,'DC C8+i','FMUL','ST(i)','ST(0)','','Valid','Valid',0,'Multiply ST(i) by ST(0) and store result\r\nin ST(i).'),(383,'DE C8+i','FMULP','ST(i)','ST(0)','','Valid','Valid',0,'Multiply ST(i) by ST(0), store result in\r\nST(i), and pop the register stack.'),(384,'DE C9','FMULP','','','','Valid','Valid',0,'Multiply ST(1) by ST(0), store result in\r\nST(1), and pop the register stack.'),(385,'DA /1','FIMUL','m32int','','','Valid','Valid',0,'Multiply ST(0) by m32int and store\r\nresult in ST(0).'),(386,'DE /1','FIMUL','m16int','','','Valid','Valid',0,'Multiply ST(0) by m16int and store\r\nresult in ST(0).'),(387,'D9 D0','FNOP','','','','Valid','Valid',0,'No operation is performed.'),(388,'D9 F3','FPATAN','','','','Valid','Valid',0,'Replace ST(1) with arctan(ST(1)/ST(0)) and pop\r\nthe register stack.'),(389,'D9 F8','FPREM','','','','Valid','Valid',0,'Replace ST(0) with the remainder obtained\r\nfrom dividing ST(0) by ST(1).'),(390,'D9 F5','FPREM1','','','','Valid','Valid',0,'Replace ST(0) with the IEEE remainder\r\nobtained from dividing ST(0) by ST(1).'),(391,'D9 F2','FPTAN','','','','Valid','Valid',0,'Replace ST(0) with its tangent and\r\npush 1 onto the FPU stack.'),(392,'D9 FC','FRNDINT','','','','Valid','Valid',0,'Round ST(0) to an integer.'),(393,'DD /4','FRSTOR','m94/108byte','','','Valid','Valid',0,'Load FPU state from\r\nm94byte or m108byte.'),(394,'9B DD /6','FSAVE','m94/108byte','','','Valid','Valid',0,'Store FPU state to m94byte or\r\nm108byte after checking for\r\npending unmasked floatingpoint\r\nexceptions. Then reinitialize\r\nthe FPU.'),(395,'DD /6','FNSAVE','m94/108byte','','','Valid','Valid',0,'Store FPU environment to\r\nm94byte or m108byte without\r\nchecking for pending unmasked\r\nfloating-point exceptions. Then\r\nre-initialize the FPU.'),(396,'D9 FD','FSCALE','','','','Valid','Valid',0,'Scale ST(0) by ST(1).'),(397,'D9 FE','FSIN','','','','Valid','Valid',0,'Replace ST(0) with its sine.\r\nTable 3-40. FSIN Results\r\nSRC (ST(0)) DEST (ST(0))\r\n−∞ *\r\n−F −1 to +1\r\n−0 −0\r\n+0 +0\r\n+F −1 to +1\r\n+• *\r\nNaN NaN\r\nNOTES:\r\nF Means finite floating-point value.\r\n* Indicates floating-point invalid-arithmetic-operand (#IA) exception.'),(398,'D9 FB','FSINCOS','','','','Valid','Valid',0,'Compute the sine and cosine of ST(0);\r\nreplace ST(0) with the sine, and push the\r\ncosine onto the register stack.'),(399,'D9 FA','FSQRT','','','','Valid','Valid',0,'Computes square root of ST(0) and stores\r\nthe result in ST(0).'),(400,'D9 /2','FST','m32fp','','','Valid','Valid',0,'Copy ST(0) to m32fp.'),(401,'DD /2','FST','m64fp','','','Valid','Valid',0,'Copy ST(0) to m64fp.'),(402,'DD D0+i','FST','ST(i)','','','Valid','Valid',0,'Copy ST(0) to ST(i).'),(403,'D9 /3','FSTP','m32fp','','','Valid','Valid',0,'Copy ST(0) to m32fp and pop register\r\nstack.'),(404,'DD /3','FSTP','m64fp','','','Valid','Valid',0,'Copy ST(0) to m64fp and pop register\r\nstack.'),(405,'DB /7','FSTP','m80fp','','','Valid','Valid',0,'Copy ST(0) to m80fp and pop register\r\nstack.'),(406,'DD D8+i','FSTP','ST(i)','','','Valid','Valid',0,'Copy ST(0) to ST(i) and pop register\r\nstack.'),(407,'9B D9 /7','FSTCW','m2byte','','','Valid','Valid',0,'Store FPU control word to m2byte\r\nafter checking for pending unmasked\r\nfloating-point exceptions.'),(408,'D9 /7','FNSTCW','m2byte','','','Valid','Valid',0,'Store FPU control word to m2byte\r\nwithout checking for pending\r\nunmasked floating-point exceptions.'),(409,'9B D9 /6','FSTENV','m14/28byte','','','Valid','Valid',0,'Store FPU environment to m14byte\r\nor m28byte after checking for\r\npending unmasked floating-point\r\nexceptions. Then mask all floatingpoint\r\nexceptions.'),(410,'D9 /6','FNSTENV','m14/28byte','','','Valid','Valid',0,'Store FPU environment to m14byte\r\nor m28byte without checking for\r\npending unmasked floating-point\r\nexceptions. Then mask all floatingpoint\r\nexceptions.'),(411,'9B DD /7','FSTSW','m2byte','','','Valid','Valid',0,'Store FPU status word at\r\nm2byte after checking for\r\npending unmasked floatingpoint\r\nexceptions.'),(412,'9B DF E0','FSTSW','AX','','','Valid','Valid',0,'Store FPU status word in AX\r\nregister after checking for\r\npending unmasked floatingpoint\r\nexceptions.'),(413,'DD /7','FNSTSW','m2byte','','','Valid','Valid',0,'Store FPU status word at\r\nm2byte without checking for\r\npending unmasked floatingpoint\r\nexceptions.'),(414,'DF E0','FNSTSW','AX','','','Valid','Valid',0,'Store FPU status word in AX\r\nregister without checking for\r\npending unmasked floatingpoint\r\nexceptions.'),(415,'D8 /4','FSUB','m32fp','','','Valid','Valid',0,'Subtract m32fp from ST(0)\r\nand store result in ST(0).'),(416,'DC /4','FSUB','m64fp','','','Valid','Valid',0,'Subtract m64fp from ST(0)\r\nand store result in ST(0).'),(417,'D8 E0+i','FSUB','ST(0)','ST(i)','','Valid','Valid',0,'Subtract ST(i) from ST(0) and\r\nstore result in ST(0).'),(418,'DC E8+i','FSUB','ST(i)','ST(0)','','Valid','Valid',0,'Subtract ST(0) from ST(i) and\r\nstore result in ST(i).'),(419,'DE E8+i','FSUBP','ST(i)','ST(0)','','Valid','Valid',0,'Subtract ST(0) from ST(i),\r\nstore result in ST(i), and pop\r\nregister stack.'),(420,'DE E9','FSUBP','','','','Valid','Valid',0,'Subtract ST(0) from ST(1),\r\nstore result in ST(1), and pop\r\nregister stack.'),(421,'DA /4','FISUB','m32int','','','Valid','Valid',0,'Subtract m32int from ST(0)\r\nand store result in ST(0).'),(422,'DE /4','FISUB','m16int','','','Valid','Valid',0,'Subtract m16int from ST(0)\r\nand store result in ST(0).'),(423,'D8 /5','FSUBR','m32fp','','','Valid','Valid',0,'Subtract ST(0) from m32fp and\r\nstore result in ST(0).'),(424,'DC /5','FSUBR','m64fp','','','Valid','Valid',0,'Subtract ST(0) from m64fp and\r\nstore result in ST(0).'),(425,'D8 E8+i','FSUBR','ST(0)','ST(i)','','Valid','Valid',0,'Subtract ST(0) from ST(i) and\r\nstore result in ST(0).'),(426,'DC E0+i','FSUBR','ST(i)','ST(0)','','Valid','Valid',0,'Subtract ST(i) from ST(0) and\r\nstore result in ST(i).'),(427,'DE E0+i','FSUBRP','ST(i)','ST(0)','','Valid','Valid',0,'Subtract ST(i) from ST(0), store\r\nresult in ST(i), and pop register\r\nstack.'),(428,'DE E1','FSUBRP','','','','Valid','Valid',0,'Subtract ST(1) from ST(0), store\r\nresult in ST(1), and pop register\r\nstack.'),(429,'DA /5','FISUBR','m32int','','','Valid','Valid',0,'Subtract ST(0) from m32int and\r\nstore result in ST(0).'),(430,'DE /5','FISUBR','m16int','','','Valid','Valid',0,'Subtract ST(0) from m16int and\r\nstore result in ST(0).'),(431,'D9 E4','FTST','','','','Valid','Valid',0,'Compare ST(0) with 0.0.'),(432,'DD E0+i','FUCOM','ST(i)','','','Valid','Valid',0,'Compare ST(0) with ST(i).'),(433,'DD E1','FUCOM','','','','Valid','Valid',0,'Compare ST(0) with ST(1).'),(434,'DD E8+i','FUCOMP','ST(i)','','','Valid','Valid',0,'Compare ST(0) with ST(i) and pop\r\nregister stack.'),(435,'DD E9','FUCOMP','','','','Valid','Valid',0,'Compare ST(0) with ST(1) and pop\r\nregister stack.'),(436,'DA E9','FUCOMPP','','','','Valid','Valid',0,'Compare ST(0) with ST(1) and pop\r\nregister stack twice.'),(437,'D9 E5','FXAM','','','','Valid','Valid',0,'Classify value or number in ST(0).'),(438,'D9 C8+i','FXCH','ST(i)','','','Valid','Valid',0,'Exchange the contents of ST(0) and\r\nST(i).'),(439,'D9 C9','FXCH','','','','Valid','Valid',0,'Exchange the contents of ST(0) and\r\nST(1).'),(440,'0F AE /1','FXRSTOR','m512byte','','','Valid','Valid',0,'Restore the x87 FPU, MMX, XMM,\r\nand MXCSR register state from\r\nm512byte.'),(441,'0F AE /0','FXSAVE','m512byte','','','Valid','Valid',0,'Save the x87 FPU, MMX, XMM,\r\nand MXCSR register state to\r\nm512byte.'),(442,'D9 F4','FXTRACT','','','','Valid','Valid',0,'Separate value in ST(0) into exponent and\r\nsignificand, store exponent in ST(0), and\r\npush the significand onto the register\r\nstack.'),(443,'D9 F1','FYL2X','','','','Valid','Valid',0,'Replace ST(1) with (ST(1) ∗ log2ST(0))\r\nand pop the register stack.'),(444,'D9 F9','FYL2XP1','','','','Valid','Valid',0,'Replace ST(1) with ST(1) ∗ log2(ST(0) +\r\n1.0) and pop the register stack.'),(445,'66 0F 7C /r','HADDPD','xmm1','xmm2/m128','','Valid','Valid',0,'Horizontal add packed doubleprecision\r\nfloating-point values\r\nfrom xmm2/m128 to xmm1.'),(446,'F2 0F 7C /r','HADDPS','xmm1','xmm2/m128','','Valid','Valid',0,'Horizontal add packed singleprecision\r\nfloating-point values from\r\nxmm2/m128 to xmm1.'),(447,'F4','HLT','','','','Valid','Valid',0,'Stops instruction execution and places the processor in a HALT state.'),(448,'66 0F 7D /r','HSUBPD','xmm1','xmm2/m128','','Valid','Valid',0,'Horizontal subtract packed doubleprecision\r\nfloating-point values from\r\nxmm2/m128 to xmm1.'),(449,'F2 0F 7D /r','HSUBPS','xmm1','xmm2/m128','','Valid','Valid',0,'Horizontal subtract packed singleprecision\r\nfloating-point values from\r\nxmm2/m128 to xmm1.'),(450,'F6 /7','IDIV','r/m8','','','Valid','Valid',0,'Signed divide AX by r/m8, with result\r\nstored in: AL ← Quotient, AH ←\r\nRemainder.'),(451,'REX + F6 /7','IDIV','r/m8','','','Valid','N.E.',0,'Signed divide AX by r/m8, with result\r\nstored in AL ← Quotient, AH ←\r\nRemainder.'),(452,'F7 /7','IDIV','r/m16','','','Valid','Valid',0,'Signed divide DX:AX by r/m16, with\r\nresult stored in AX ← Quotient, DX ←\r\nRemainder.'),(453,'F7 /7','IDIV','r/m32','','','Valid','Valid',0,'Signed divide EDX:EAX by r/m32, with\r\nresult stored in EAX ← Quotient, EDX\r\n← Remainder.'),(454,'REX.W + F7 /7','IDIV','r/m64','','','Valid','N.E.',0,'Signed divide RDX:RAX by r/m64, with\r\nresult stored in RAX ← Quotient, RDX\r\n← Remainder.'),(455,'F6 /5','IMUL','r/m8','','','Valid','Valid',0,'AX← AL ∗ r/m byte.'),(456,'F7 /5','MUL','r/m16','','','Valid','Valid',0,'DX:AX ← AX ∗ r/m word.'),(457,'F7 /5','IMUL','r/m32','','','Valid','Valid',0,'EDX:EAX ← EAX ∗ r/m32.'),(458,'REX.W + F7 /5','IMUL','r/m64','','','Valid','N.E.',0,'RDX:RAX ← RAX ∗ r/m64.'),(459,'0F AF /r','IMUL','r16','r/m16','','Valid','Valid',0,'word register ← word register ∗\r\nr/m16.'),(460,'0F AF /r','IMUL','r32','r/m32','','Valid','Valid',0,'doubleword register ←\r\ndoubleword register ∗ r/m32.'),(461,'REX.W + 0F AF /r','IMUL','r64','r/m64','','Valid','N.E.',0,'Quadword register ← Quadword\r\nregister ∗ r/m64.'),(462,'6B /r ib','IMUL','r16','r/m16','imm8','Valid','Valid',0,'word register ← r/m16 ∗ signextended\r\nimmediate byte.'),(463,'6B /r ib','IMUL','r32','r/m32','imm8','Valid','Valid',0,'doubleword register ← r/m32 ∗\r\nsign-extended immediate byte.'),(464,'REX.W + 6B /r ib','IMUL','r64','r/m64','imm8','Valid','N.E.',0,'Quadword register ← r/m64 ∗\r\nsign-extended immediate byte.'),(465,'6B /r ib','IMUL','r16','imm8','','Valid','Valid',0,'word register ← word register ∗\r\nsign-extended immediate byte.'),(466,'6B /r ib','IMUL','r32','imm8','','Valid','Valid',0,'doubleword register ←\r\ndoubleword register ∗ signextended\r\nimmediate byte.'),(467,'REX.W + 6B /r ib','IMUL','r64','imm8','','Valid','N.E.',0,'Quadword register ← Quadword\r\nregister ∗ sign-extended\r\nimmediate byte.'),(468,'69 /r iw','IMUL','r16','r/m16','imm16','Valid','Valid',0,'word register ← r/m16 ∗\r\nimmediate word.'),(469,'69 /r id','IMUL','r32','r/m32','imm32','Valid','Valid',0,'doubleword register ← r/m32 ∗\r\nimmediate doubleword.'),(470,'REX.W + 69 /r id','IMUL','r64','r/m64','imm32','Valid','N.E.',0,'Quadword register ← r/m64 ∗\r\nimmediate doubleword.'),(471,'69 /r iw','IMUL','r16','imm16','','Valid','Valid',0,'word register ← r/m16 ∗\r\nimmediate word.'),(472,'69 /r id','IMUL','r32','imm32','','Valid','Valid',0,'doubleword register ← r/m32 ∗'),(473,'69 /r id','MUL','r32','imm32','','Valid','Valid',0,'doubleword register ← r/m32 ∗\r\nimmediate doubleword.'),(474,'REX.W + 69 /r id','IMUL','r64','imm32','','Valid','N.E.',0,'Quadword register ← r/m64 ∗\r\nimmediate doubleword.'),(475,'E4 ib','IN','AL','imm8','','Valid','Valid',0,'Input byte from imm8 I/O port address into\r\nAL.'),(476,'E5 ib','IN','AX','imm8','','Valid','Valid',0,'Input word from imm8 I/O port address into\r\nAX.'),(477,'E5 ib','IN','EAX','imm8','','Valid','Valid',0,'Input dword from imm8 I/O port address into\r\nEAX.'),(478,'EC','IN','AL','DX','','Valid','Valid',0,'Input byte from I/O port in DX into AL.'),(479,'ED','IN','AX','DX','','Valid','Valid',0,'Input byte from I/O port in DX into AL.'),(480,'ED','IN','AX','DX','','Valid','Valid',0,'Input word from I/O port in DX into AX.'),(481,'ED','IN','EAX','DX','','Valid','Valid',0,'Input doubleword from I/O port in DX into\r\nEAX.'),(482,'FE /0','INC','r/m8','','','Valid','Valid',0,'Increment r/m byte by 1.'),(483,'REX + FE /0','INC','r/m8','','','Valid','N.E.',0,'Increment r/m byte by 1.'),(484,'FF /0','INC','r/m16','','','Valid','Valid',0,'Increment r/m word by 1.'),(485,'FF /0','INC','r/m32','','','Valid','Valid',0,'Increment r/m doubleword by 1.'),(486,'REX.W + FF /0','INC','r/m64','','','Valid','N.E.',0,'Increment r/m quadword by 1.'),(487,'40+ rw','INC','r16','','','N.E.','Valid',0,'Increment word register by 1.'),(488,'40+ rd','INC','r32','','','N.E.','Valid',0,'Increment doubleword register by 1.'),(489,'6C','INS','m8','DX','','Valid','Valid',0,'Input byte from I/O port specified in DX\r\ninto memory location specified in ES:(E)DI\r\nor RDI.'),(490,'6D','INS','m16','DX','','Valid','Valid',0,'Input word from I/O port specified in DX\r\ninto memory location specified in ES:(E)DI\r\nor RDI.'),(491,'6D','INS','m32','DX','','Valid','Valid',0,'Input doubleword from I/O port specified\r\nin DX into memory location specified in\r\nES:(E)DI or RDI.'),(492,'6C','INSB','','','','Valid','Valid',0,'Input byte from I/O port specified in DX\r\ninto memory location specified with\r\nES:(E)DI or RDI.'),(493,'6D','INSW','','','','Valid','Valid',0,'Input word from I/O port specified in DX\r\ninto memory location specified in ES:(E)DI\r\nor RDI.'),(494,'6D','INSD','','','','Valid','Valid',0,'Input doubleword from I/O port specified\r\nin DX into memory location specified in\r\nES:(E)DI or RDI.'),(495,'CC','INT','3','','','Valid','Valid',0,'Interrupt 3—trap to debugger.'),(496,'CD ib','INT','imm8','','','Valid','Valid',0,'Interrupt vector number specified by\r\nimmediate byte.'),(497,'CE','INTO','','','','Invalid','Valid',0,'Interrupt 4—if overflow flag is 1.'),(498,'0F 08','INVD','','','','Valid','Valid',0,'Flush internal caches; initiate flushing of\r\nexternal caches.'),(499,'0F 01/7','INVLPG','m','','','Valid','Valid',0,'Invalidate TLB Entry for page that\r\ncontains m.'),(500,'CF','IRET','','','','Valid','Valid',0,'Interrupt return (16-bit operand\r\nsize).'),(501,'CF','IRETD','','','','Valid','Valid',0,'Interrupt return (32-bit operand\r\nsize).'),(502,'REX.W + CF','IRETQ','','','','Valid','N.E.',0,'Interrupt return (64-bit operand\r\nsize).'),(503,'77 cb','JA','rel8','','','Valid','Valid',0,'Jump short if above (CF=0 and ZF=0).'),(504,'73 cb','JAE','rel8','','','Valid','Valid',0,'Jump short if above or equal (CF=0).'),(505,'72 cb','JB','rel8','','','Valid','Valid',0,'Jump short if below (CF=1).'),(506,'76 cb','JBE','rel8','','','Valid','Valid',0,'Jump short if below or equal (CF=1 or\r\nZF=1).'),(507,'72 cb','JC','rel8','','','Valid','Valid',0,'Jump short if carry (CF=1).'),(508,'E3 cb','JCXZ','rel8','','','N.E.','Valid',0,'Jump short if CX register is 0.'),(509,'E3 cb','JECXZ','rel8','','','Valid','Valid',0,'Jump short if ECX register is 0.'),(510,'E3 cb','JRCXZ','rel8','','','Valid','N.E.',0,'Jump short if RCX register is 0.'),(511,'74 cb','JE','rel8','','','Valid','Valid',0,'Jump short if equal (ZF=1).'),(512,'7F cb','JG','rel8','','','Valid','Valid',0,'Jump short if greater (ZF=0 and SF=OF).'),(513,'7D cb','JGE','rel8','','','Valid','Valid',0,'Jump short if greater or equal (SF=OF).'),(514,'7C cb','JL','rel8','','','Valid','Valid',0,'Jump short if less (SF≠ OF).'),(515,'7E cb','JLE','rel8','','','Valid','Valid',0,'Jump short if less or equal (ZF=1 or SF≠\r\nOF).'),(516,'76 cb','JNA','rel8','','','Valid','Valid',0,'Jump short if not above (CF=1 or ZF=1).'),(517,'72 cb','JNAE','rel8','','','Valid','Valid',0,'Jump short if not above or equal (CF=1).'),(518,'73 cb','JNB','rel8','','','Valid','Valid',0,'Jump short if not below (CF=0).'),(519,'77 cb','JNBE','rel8','','','Valid','Valid',0,'Jump short if not below or equal (CF=0\r\nand ZF=0).'),(520,'73 cb','JNC','rel8','','','Valid','Valid',0,'Jump short if not carry (CF=0).'),(521,'75 cb','JNE','rel8','','','Valid','Valid',0,'Jump short if not equal (ZF=0).'),(522,'7E cb','JNG','rel8','','','Valid','Valid',0,'Jump short if not greater (ZF=1 or SF≠\r\nOF).'),(523,'7C cb','JNGE','rel8','','','Valid','Valid',0,'Jump short if not greater or equal (SF≠\r\nOF).'),(524,'7D cb','JNL','rel8','','','Valid','Valid',0,'Jump short if not less (SF=OF).'),(525,'7F cb','JNLE','rel8','','','Valid','Valid',0,'Jump short if not less or equal (ZF=0 and\r\nSF=OF).'),(526,'71 cb','JNO','rel8','','','Valid','Valid',0,'Jump short if not overflow (OF=0).'),(527,'7B cb','JNP','rel8','','','Valid','Valid',0,'Jump short if not parity (PF=0).'),(528,'79 cb','JNS','rel8','','','Valid','Valid',0,'Jump short if not sign (SF=0).'),(529,'75 cb','JNZ','rel8','','','Valid','Valid',0,'Jump short if not zero (ZF=0).'),(530,'70 cb','JO','rel8','','','Valid','Valid',0,'Jump short if overflow (OF=1).'),(531,'7A cb','JP','rel8','','','Valid','Valid',0,'Jump short if parity (PF=1).'),(532,'7A cb','JPE','rel8','','','Valid','Valid',0,'Jump short if parity even (PF=1).'),(533,'7B cb','JPO','rel8','','','Valid','Valid',0,'Jump short if parity odd (PF=0).'),(534,'78 cb','JS','rel8','','','Valid','Valid',0,'Jump short if sign (SF=1).'),(535,'74 cb','JZ','rel8','','','Valid','Valid',0,'Jump short if zero (ZF ← 1).'),(536,'0F 87 cw','JA','rel16','','','N.S.','Valid',0,'Jump near if above (CF=0 and ZF=0). Not\r\nsupported in 64-bit mode.'),(537,'0F 87 cd','JA','rel32','','','Valid','Valid',0,'Jump near if above (CF=0 and ZF=0).'),(538,'0F 83 cw','JAE','rel16','','','N.S','Valid',0,'Jump near if above or equal (CF=0). Not\r\nsupported in 64-bit mode.'),(539,'0F 83 cd','JAE','rel32','','','Valid','Valid',0,'Jump near if above or equal (CF=0).'),(540,'0F 82 cw','JB','rel16','','','N.S.','Valid',0,'Jump near if below (CF=1). Not supported\r\nin 64-bit mode.'),(541,'0F 82 cd','JB','rel32','','','Valid','Valid',0,'Jump near if below (CF=1).'),(542,'0F 86 cw','JBE','rel16','','','N.S.','Valid',0,'Jump near if below or equal (CF=1 or\r\nZF=1). Not supported in 64-bit mode.'),(543,'0F 86 cd','JBE','rel32','','','Valid','Valid',0,'Jump near if below or equal (CF=1 or\r\nZF=1).'),(544,'0F 82 cw','JC','rel16','','','N.S.','Valid',0,'Jump near if carry (CF=1). Not supported\r\nin 64-bit mode.'),(545,'0F 82 cd','JC','rel32','','','Valid','Valid',0,'Jump near if carry (CF=1).'),(546,'0F 84 cw','JE','rel16','','','N.S.','Valid',0,'Jump near if equal (ZF=1). Not supported\r\nin 64-bit mode.'),(547,'0F 84 cd','JE','rel32','','','Valid','Valid',0,'Jump near if equal (ZF=1).'),(548,'0F 84 cw','JZ','rel16','','','N.S.','Valid',0,'Jump near if 0 (ZF=1). Not supported in\r\n64-bit mode.'),(549,'0F 84 cd','JZ','rel32','','','Valid','Valid',0,'Jump near if 0 (ZF=1).'),(550,'0F 8F cw','JG','rel16','','','N.S.','Valid',0,'Jump near if greater (ZF=0 and SF=OF).\r\nNot supported in 64-bit mode.'),(551,'0F 8F cd','JG','rel32','','','Valid','Valid',0,'Jump near if greater (ZF=0 and SF=OF).'),(552,'0F 8D cw','JGE','rel16','','','N.S.','Valid',0,'Jump near if greater or equal (SF=OF).\r\nNot supported in 64-bit mode.'),(553,'0F 8D cd','JGE','rel32','','','Valid','Valid',0,'Jump near if greater or equal (SF=OF).'),(554,'0F 8C cw','JL','rel16','','','N.S.','Valid',0,'Jump near if less (SF≠ OF). Not supported\r\nin 64-bit mode.'),(555,'0F 8C cd','JL','rel32','','','Valid','Valid',0,'Jump near if less (SF≠ OF).'),(556,'0F 8E cw','JLE','rel16','','','N.S.','Valid',0,'Jump near if less or equal (ZF=1 or SF≠\r\nOF). Not supported in 64-bit mode.'),(557,'0F 8E cd','JLE rel32','','','','Valid','Valid',0,'Jump near if less or equal (ZF=1 or SF≠\r\nOF).'),(558,'0F 86 cw','JNA','rel16','','','N.S.','Valid',0,'Jump near if not above (CF=1 or ZF=1).\r\nNot supported in 64-bit mode.'),(559,'0F 86 cd','JNA','rel32','','','Valid','Valid',0,'Jump near if not above (CF=1 or ZF=1).'),(560,'0F 82 cw','JNAE','rel16','','','N.S.','Valid',0,'Jump near if not above or equal (CF=1).\r\nNot supported in 64-bit mode.'),(561,'0F 82 cd','JNAE','rel32','','','Valid','Valid',0,'Jump near if not above or equal (CF=1).'),(562,'0F 83 cw','JNB','rel16','','','N.S.','Valid',0,'Jump near if not below (CF=0). Not\r\nsupported in 64-bit mode.'),(563,'0F 83 cd','JNB','rel32','','','Valid','Valid',0,'Jump near if not below (CF=0).'),(564,'0F 87 cw','JNBE','rel16','','','N.S.','Valid',0,'Jump near if not below or equal (CF=0\r\nand ZF=0). Not supported in 64-bit\r\nmode.'),(565,'0F 87 cd','JNBE','rel32','','','Valid','Valid',0,'Jump near if not below or equal (CF=0\r\nand ZF=0).'),(566,'0F 83 cw','JNC','rel16','','','N.S.','Valid',0,'Jump near if not carry (CF=0). Not\r\nsupported in 64-bit mode.'),(567,'0F 83 cd','JNC','rel32','','','Valid','Valid',0,'Jump near if not carry (CF=0).'),(568,'0F 85 cw','JNE','rel16','','','N.S.','Valid',0,'Jump near if not equal (ZF=0). Not\r\nsupported in 64-bit mode.'),(569,'0F 85 cd','JNE','rel32','','','Valid','Valid',0,'Jump near if not equal (ZF=0).'),(570,'0F 8E cw','JNG','rel16','','','N.S.','Valid',0,'Jump near if not greater (ZF=1 or SF≠\r\nOF). Not supported in 64-bit mode.'),(571,'0F 8E cd','JNG','rel32','','','Valid','Valid',0,'Jump near if not greater (ZF=1 or SF≠\r\nOF).'),(572,'0F 8C cw','JNGE','rel16','','','N.S.','Valid',0,'Jump near if not greater or equal (SF≠\r\nOF). Not supported in 64-bit mode.'),(573,'0F 8C cd','JNGE','rel32','','','Valid','Valid',0,'Jump near if not greater or equal (SF≠\r\nOF).'),(574,'0F 8D cw','JNL','rel16','','','N.S.','Valid',0,'Jump near if not less (SF=OF). Not\r\nsupported in 64-bit mode.'),(575,'0F 8D cd','JNL','rel32','','','Valid','Valid',0,'Jump near if not less (SF=OF).'),(576,'0F 8F cd','JNLE','rel32','','','Valid','Valid',0,'Jump near if not less or equal (ZF=0 and\r\nSF=OF).'),(577,'0F 81 cw','JNO','rel16','','','N.S.','Valid',0,'Jump near if not overflow (OF=0). Not\r\nsupported in 64-bit mode.'),(578,'0F 81 cd','JNO','rel32','','','Valid','Valid',0,'Jump near if not overflow (OF=0).'),(579,'0F 8B cw','JNP','rel16','','','N.S.','Valid',0,'Jump near if not parity (PF=0). Not\r\nsupported in 64-bit mode.'),(580,'0F 8B cd','JNP','rel32','','','Valid','Valid',0,'Jump near if not parity (PF=0).'),(581,'0F 89 cw','JNS','rel16','','','N.S.','Valid',0,'Jump near if not sign (SF=0). Not\r\nsupported in 64-bit mode.'),(582,'0F 89 cd','JNS','rel32','','','Valid','Valid',0,'Jump near if not sign (SF=0).'),(583,'0F 85 cw','JNZ','rel16','','','N.S.','Valid',0,'Jump near if not zero (ZF=0). Not\r\nsupported in 64-bit mode.'),(584,'0F 85 cd','JNZ','rel32','','','Valid','Valid',0,'Jump near if not zero (ZF=0).'),(585,'0F 80 cw','JO','rel16','','','N.S.','Valid',0,'Jump near if overflow (OF=1). Not\r\nsupported in 64-bit mode.'),(586,'0F 80 cd','JO','rel32','','','Valid','Valid',0,'Jump near if overflow (OF=1).'),(587,'0F 8A cw','0F 8A cw','rel16','','','N.S.','Valid',0,'Jump near if parity (PF=1). Not supported\r\nin 64-bit mode.'),(588,'0F 8A cd','JP','rel32','','','Valid','Valid',0,'Jump near if parity (PF=1).'),(589,'0F 8A cw','JPE','rel16','','','N.S.','Valid',0,'Jump near if parity even (PF=1). Not\r\nsupported in 64-bit mode.'),(590,'0F 8A cd','JPE','rel32','','','Valid','Valid',0,'Jump near if parity even (PF=1).'),(591,'0F 8B cw','JPO','rel16','','','N.S.','Valid',0,'Jump near if parity odd (PF=0). Not\r\nsupported in 64-bit mode.'),(592,'0F 8B cd','JPO','rel32','','','Valid','Valid',0,'Jump near if parity odd (PF=0).'),(593,'0F 88 cw','JS','rel16','','','N.S.','Valid',0,'Jump near if sign (SF=1). Not supported\r\nin 64-bit mode.'),(594,'0F 88 cd','JS','rel32','','','Valid','Valid',0,'Jump near if sign (SF=1).'),(595,'0F 84 cw','JZ','rel16','','','N.S.','Valid',0,'Jump near if 0 (ZF=1). Not supported in\r\n64-bit mode.'),(596,'0F 84 cd','JZ','rel32','','','Valid','Valid',0,'Jump near if 0 (ZF=1).'),(597,'EB cb','JMP','rel8','','','Valid','Valid',0,'Jump short, RIP = RIP + 8-bit displacement\r\nsign extended to 64-bits'),(598,'E9 cw','JMP','rel16','','','N.S.','Valid',0,'Jump near, relative, displacement relative\r\nto next instruction. Not supported in 64-bit\r\nmode.'),(599,'E9 cd','JMP','rel32','','','Valid','Valid',0,'Jump near, relative, RIP = RIP + 32-bit\r\ndisplacement sign extended to 64-bits'),(600,'FF /4','JMP','r/m16','','','N.S.','Valid',0,'Jump near, absolute indirect, address =\r\nsign-extended r/m16. Not supported in 64-\r\nbit mode.'),(601,'FF /4','JMP','r/m32','','','N.S.','Valid',0,'Jump near, absolute indirect, address =\r\nsign-extended r/m32. Not supported in 64-\r\nbit mode.'),(602,'FF /4','JMP','r/m64','','','Valid','N.E.',0,'Jump near, absolute indirect, RIP = 64-Bit\r\noffset from register or memory'),(603,'EA cd','JMP','ptr16:16','','','Inv.','Valid',0,'Jump far, absolute, address given in\r\noperand'),(604,'EA cp','JMP','ptr16:32','','','Inv.','Valid',0,'Jump far, absolute, address given in\r\noperand'),(605,'FF /5','JMP','m16:16','','','Valid','Valid',0,'Jump far, absolute indirect, address given in\r\nm16:16'),(606,'FF /5','JMP','m16:32','','','Valid','Valid',0,'Jump far, absolute indirect, address given in\r\nm16:32.'),(607,'REX.W + FF /5','JMP','m16:64','','','Valid','N.E.',0,'Jump far, absolute indirect, address given in\r\nm16:64.'),(608,'9F','LAHF','','','','Invalid','Valid',0,'Load: AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF).'),(609,'0F 02 /r','LAR','r16','r16/m16','','Valid','Valid',0,'r16 ← r16/m16 masked by\r\nFF00H.'),(610,'0F 02 /r','LAR','r32','r32/m16','','Valid','Valid',0,'r32 ← r32/m16 masked by\r\n00FxFF00H'),(611,'REX.W + 0F 02 /r','LAR','r64','r32/m16','','Valid','N.E.',0,'r64 ← r32/m16 masked by\r\n00FxFF00H and zero extended'),(612,'F2 0F F0 /r','LDDQU','xmm1','mem','','Valid','Valid',0,'Load unaligned data from mem\r\nand return double quadword in\r\nxmm1.'),(613,'0F AE /2','LDMXCSR','m32','','','Valid','Valid',0,'Load MXCSR register from m32. (Opcode in Intel Manual shows 0F,AE,/2 as the opcode, however the commas appear to be a typo)'),(614,'C5 /r','LDS','r16','m16:16','','Invalid','Valid',0,'Load DS:r16 with far pointer from\r\nmemory.'),(615,'C5 /r','LDS','r32','m16:32','','Invalid','Valid',0,'Load DS:r32 with far pointer from\r\nmemory.'),(616,'0F B2 /r','LSS','r16','m16:16','','Valid','Valid',0,'Load SS:r16 with far pointer from\r\nmemory.'),(617,'0F B2 /r','LSS','r32','m16:32','','Valid','Valid',0,'Load SS:r32 with far pointer from\r\nmemory.'),(618,'REX + 0F B2 /r','LSS','r64','m16:64','','Valid','N.E.',0,'Load SS:r64 with far pointer from\r\nmemory.'),(619,'C4 /r','LES','r16','m16:16','','Invalid','Valid',0,'Load ES:r16 with far pointer from\r\nmemory.'),(620,'C4 /r','LES','r32','m16:32','','Invalid','Valid',0,'Load ES:r32 with far pointer from\r\nmemory.'),(621,'0F B4 /r','LFS','r16','m16:16','','Valid','Valid',0,'Load FS:r16 with far pointer from\r\nmemory.'),(622,'0F B4 /r','LFS','r32','m16:32','','Valid','Valid',0,'Load FS:r32 with far pointer from\r\nmemory.'),(623,'REX + 0F B4 /r','LFS','r64','m16:64','','Valid','N.E.',0,'Load FS:r64 with far pointer from\r\nmemory.'),(624,'0F B5 /r','LGS','r16','m16:16','','Valid','Valid',0,'Load GS:r16 with far pointer from\r\nmemory.'),(625,'0F B5 /r','LGS','r32','m16:32','','Valid','Valid',0,'Load GS:r32 with far pointer from\r\nmemory.'),(626,'REX + 0F B5 /r','LGS','r64','m16:64','','Valid','N.E.',0,'Load GS:r64 with far pointer from\r\nmemory.'),(627,'8D /r','LEA','r16','m','','Valid','Valid',0,'Store effective address for m in register\r\nr16.'),(628,'8D /r','LEA','r32','m','','Valid','Valid',0,'Store effective address for m in register\r\nr32.'),(629,'REX.W + 8D /r','LEA','r64','m','','Valid','N.E.',0,'Store effective address for m in register\r\nr64.'),(630,'C9','LEAVE','','','','Valid','Valid',0,'Set SP to BP, then pop BP.'),(631,'C9','LEAVE','','','','N.E.','Valid',0,'Set ESP to EBP, then pop EBP.'),(632,'C9','LEAVE','','','','Valid','N.E.',0,'Set RSP to RBP, then pop RBP.'),(633,'0F AE /5','LFENCE','','','','Valid','Valid',0,'Serializes load operations.'),(634,'0F 01 /2','LGDT','m16&32','','','N.E.','Valid',0,'Load m into GDTR.'),(635,'0F 01 /3','LIDT','m16&32','','','N.E.','Valid',0,'Load m into IDTR.'),(636,'0F 01 /2','LIDT','m16&64','','','Valid','N.E.',0,'Load m into IDTR.'),(637,'0F 00 /2','LLDT','r/m16','','','Valid','Valid',0,'Load segment selector r/m16 into\r\nLDTR.'),(638,'0F 01 /6','LMSW','r/m16','','','Valid','Valid',0,'Loads r/m16 in machine status word\r\nof CR0.'),(639,'F0','LOCK','','','','Valid','Valid',0,'Asserts LOCK# signal for duration\r\nthe accompanying instruction.'),(640,'AC','LODS','m8','','','Valid','Valid',0,'For legacy mode, Load byte at address\r\nDS:(E)SI into AL. For 64-bit mode load byte\r\nat address (R)SI into AL.'),(641,'AD','LODS','m16','','','Valid','Valid',0,'For legacy mode, Load word at address\r\nDS:(E)SI into AX. For 64-bit mode load\r\nword at address (R)SI into AX.'),(642,'AD','LODS','m32','','','Valid','Valid',0,'For legacy mode, Load dword at address\r\nDS:(E)SI into EAX. For 64-bit mode load\r\ndword at address (R)SI into EAX.'),(643,'REX.W + AD','LODS','m64','','','Valid','N.E.',0,'Load qword at address (R)SI into RAX.'),(644,'AC','LODSB','','','','Valid','Valid',0,'For legacy mode, Load byte at address\r\nDS:(E)SI into AL. For 64-bit mode load byte\r\nat address (R)SI into AL.'),(645,'AD','LODSW','','','','Valid','Valid',0,'For legacy mode, Load word at address\r\nDS:(E)SI into AX. For 64-bit mode load\r\nword at address (R)SI into AX.'),(646,'AD','LODSD','','','','Valid','Valid',0,'For legacy mode, Load dword at address\r\nDS:(E)SI into EAX. For 64-bit mode load\r\ndword at address (R)SI into EAX.'),(647,'REX.W + AD','LODSQ','','','','Valid','N.E.',0,'Load qword at address (R)SI into RAX.'),(648,'E2 cb','LOOP','rel8','','','Valid','Valid',0,'Decrement count; jump short if count ≠ 0.'),(649,'E1 cb','LOOPE','rel8','','','Valid','Valid',0,'Decrement count; jump short if count ≠ 0\r\nand ZF = 1.'),(650,'E0 cb','LOOPNE','rel8','','','Valid','Valid',0,'Decrement count; jump short if count ≠ 0\r\nand ZF = 0.'),(651,'0F 03 /r','LSL','r16','r16/m16','','Valid','Valid',0,'Load: r16 ← segment limit,\r\nselector r16/m16.'),(652,'0F 03 /r','LSL','r32','r32/m16','','Valid','Valid',0,'Load: r32 ← segment limit,'),(653,'REX.W + 0F 03 /r','LSL','r64','r32/m16','','Valid','Valid',0,'Load: r64 ← segment limit,\r\nselector r32/m16'),(654,'0F 00 /3','LTR','r/m16','','','Valid','Valid',0,'Load r/m16 into task register.'),(655,'66 0F F7 /r','MASKMOVDQU','xmm1','xmm2','','Valid','Valid',0,'Selectively write bytes from xmm1 to\r\nmemory location using the byte mask in\r\nxmm2. The default memory location is\r\nspecified by DS:EDI.'),(656,'0F F7 /r','MASKMOVQ','mm1','mm2','','Valid','Valid',0,'Selectively write bytes from mm1 to\r\nmemory location using the byte mask in\r\nmm2. The default memory location is\r\nspecified by DS:EDI.'),(657,'66 0F 5F /r','MAXPD','xmm1','xmm2/m128','','Valid','Valid',0,'Return the maximum doubleprecision\r\nfloating-point values\r\nbetween xmm2/m128 and xmm1.'),(658,'0F 5F /r','MAXPS','xmm1','xmm2/m128','','Valid','Valid',0,'Return the maximum single-precision\r\nfloating-point values between\r\nxmm2/m128 and xmm1.'),(659,'F2 0F 5F /r','MAXSD','xmm1','xmm2/m64','','Valid','Valid',0,'Return the maximum scalar doubleprecision\r\nfloating-point value\r\nbetween xmm2/mem64 and xmm1.'),(660,'F3 0F 5F /r','MAXSS','xmm1','xmm2/m32','','Valid','Valid',0,'Return the maximum scalar singleprecision\r\nfloating-point value\r\nbetween xmm2/mem32 and\r\nxmm1.'),(661,'0F AE /6','MFENCE','','','','Valid','Valid',0,'Serializes load and store operations.'),(662,'66 0F 5D /r','MINPD','xmm1','xmm2/m128','','Valid','Valid',0,'Return the minimum doubleprecision\r\nfloating-point values\r\nbetween xmm2/m128 and xmm1.'),(663,'0F 5D /r','MINPS','xmm1','xmm2/m128','','Valid','Valid',0,'Return the minimum single-precision\r\nfloating-point values between\r\nxmm2/m128 and xmm1.'),(664,'F2 0F 5D /r','MINSD','xmm1','xmm2/m64','','Valid','Valid',0,'Return the minimum scalar doubleprecision\r\nfloating-point value\r\nbetween xmm2/mem64 and xmm1.'),(665,'F3 0F 5D /r','MINSS','xmm1','xmm2/m32','','Valid','Valid',0,'Return the minimum scalar singleprecision\r\nfloating-point value\r\nbetween xmm2/mem32 and\r\nxmm1.'),(666,'OF 01 C8','MONITOR','','','','Valid','Valid',0,'Sets up a linear address range to be\r\nmonitored by hardware and activates\r\nthe monitor. The address range should\r\nbe a write-back memory caching type.\r\nThe default address is DS:EAX.'),(667,'88 /r','MOV','r/m8','r8','','Valid','Valid',0,'Move r8 to r/m8.'),(668,'REX + 88 /r','MOV','r/m8','r8','','Valid','N.E.',0,'Move r8 to r/m8.'),(669,'89 /r','MOV','r/m16','r16','','Valid','Valid',0,'Move r16 to r/m16.'),(670,'89 /r','MOV','r/m32','r32','','Valid','Valid',0,'Move r32 to r/m32.'),(671,'REX.W + 89 /r','MOV','r/m64','r64','','Valid','N.E.',0,'Move r64 to r/m64.'),(672,'8A /r','MOV','r8','r/m8','','Valid','Valid',0,'Move r/m8 to r8.'),(673,'REX + 8A /r','MOV','r8','r/m8','','Valid','N.E.',0,'Move r/m8 to r8.'),(674,'8B /r','MOV','r16','r/m16','','Valid','Valid',0,'Move r/m16 to r16.'),(675,'8B /r','MOV','r32','r/m32','','Valid','Valid',0,'Move r/m32 to r32.'),(676,'REX.W + 8B /r','MOV','r64','r/m64','','Valid','N.E.',0,'Move r/m64 to r64.'),(677,'8C /r','MOV','r/m16','Sreg','','Valid','Valid',0,'Move segment register to\r\nr/m16.'),(678,'REX.W + 8C /r','MOV','r/m64','Sreg','','Valid','Valid',0,'Move zero extended 16-bit\r\nsegment register to r/m64.'),(679,'8E /r','MOV','Sreg','r/m16','','Valid','Valid',0,'Move r/m16 to segment\r\nregister.'),(680,'REX.W + 8E /r','MOV','Sreg','r/m64','','Valid','Valid',0,'Move lower 16 bits of\r\nr/m64 to segment register.'),(681,'A0','MOV','AL','moffs8','','Valid','Valid',0,'Move byte at (seg:offset)\r\nto AL.'),(682,'REX.W + A0','MOV','AL','moffs8','','Valid','N.E.',0,'Move byte at (offset) to\r\nAL.'),(683,'A1','MOV','AX','moffs16','','Valid','Valid',0,'Move word at (seg:offset)\r\nto AX.'),(684,'A1','MOV','EAX','moffs32','','Valid','Valid',0,'Move doubleword at\r\n(seg:offset) to EAX.'),(685,'REX.W + A1','MOV','RAX','moffs64','','Valid','N.E.',0,'Move quadword at (offset)\r\nto RAX.'),(686,'A2','MOV','moffs8','AL','','Valid','Valid',0,'Move AL to (seg:offset).'),(687,'REX.W + A2','MOV','moffs8','AL','','Valid','Valid',0,'Move AL to (seg:offset).'),(688,'REX.W + A2','MOV','moffs8','AL','','Valid','N.E.',0,'Move AL to (offset).'),(689,'A3','MOV','moffs16','AX','','Valid','Valid',0,'Move AX to (seg:offset).'),(690,'A3','MOV','moffs32','EAX','','Valid','Valid',0,'Move EAX to (seg:offset).'),(691,'REX.W + A3','MOV','moffs64','RAX','','Valid','N.E.',0,'Move RAX to (offset).'),(692,'B0+ rb','MOV','r8','imm8','','Valid','Valid',0,'Move imm8 to r8.'),(693,'REX + B0+ rb','MOV','r8','imm8','','Valid','N.E.',0,'Move imm8 to r8.'),(694,'B8+ rw','MOV','r16','imm16','','Valid','Valid',0,'Move imm16 to r16.'),(695,'B8+ rd','MOV','r32','imm32','','Valid','Valid',0,'Move imm32 to r32.'),(696,'REX.W + B8+ rd','MOV','r64','imm64','','Valid','N.E.',0,'Move imm64 to r64.'),(697,'C6 /0','MOV','r/m8','imm8','','Valid','Valid',0,'Move imm8 to r/m8.'),(698,'REX + C6 /0','MOV','r/m8','imm8','','imm8','N.E.',0,'Move imm8 to r/m8.'),(699,'C7 /0','MOV','r/m16','imm16','','Valid','Valid',0,'Move imm16 to r/m16.'),(700,'C7 /0','MOV','r/m32','imm32','','Valid','Valid',0,'Move imm32 to r/m32.'),(701,'REX.W + C7 /0','MOV','r/m64','imm32','','Valid','N.E.',0,'Move imm32 sign\r\nextended to 64-bits to\r\nr/m64.'),(702,'0F 20 /0','MOV','r32','CR0','','N.E.','Valid',0,'Move CR0 to r32.'),(703,'0F 20 /0','MOV','r64','CR0','','Valid','N.E.',0,'Move extended CR0 to r64.'),(704,'0F 20 /2','MOV','r32','CR2','','N.E.','Valid',0,'Move CR2 to r32.'),(705,'0F 20 /2','MOV','r64','CR2','','Valid','N.E.',0,'Move extended CR2 to r64.'),(706,'0F 20 /3','MOV','r32','CR3','','N.E.','Valid',0,'Move CR3 to r32.'),(707,'0F 20 /3','MOV','r64','CR3','','Valid','N.E.',0,'Move extended CR3 to r64.'),(708,'0F 20 /4','MOV','r64','CR4','','Valid','N.E.',0,'Move extended CR4 to r64.'),(709,'REX.R + 0F 20 /0','MOV','r64','CR8','','Valid','N.E.',0,'Move extended CR8 to r64.'),(710,'0F 22 /0','MOV','CR0','r32','','N.E.','Valid',0,'Move r32 to CR0.'),(711,'0F 22 /0','MOV','CR0','r64','','Valid','N.E.',0,'Move r64 to extended CR0.'),(712,'0F 22 /2','MOV','CR2','r32','','N.E.','Valid',0,'Move r32 to CR2.'),(713,'0F 22 /2','MOV','CR2','r64','','Valid','N.E.',0,'Move r64 to extended CR2.'),(714,'0F 22 /3','MOV','CR3','r32','','N.E.','Valid',0,'Move r32 to CR3.'),(715,'0F 22 /3','MOV','CR3','r64','','Valid','N.E',0,'Move r64 to extended CR3.'),(716,'0F 22 /4','MOV','CR4','r32','','N.E.','Valid',0,'Move r32 to CR4.'),(717,'0F 22 /4','MOV','CR4','r64','','Valid','N.E.',0,'Move r64 to extended CR4.'),(718,'REX.R + 0F 22 /0','MOV','CR8','r64','','Valid','N.E.',0,'Move r64 to extended CR8.'),(719,'0F 21/r','MOV','r32','DR0-DR7','','N.E.','Valid',0,'Move debug register to r32'),(720,'0F 21/r','MOV','r64','DR0-DR7','','Valid','N.E.',0,'Move extended debug register\r\nto r64.'),(721,'0F 23 /r','MOV','DR0-DR7','r32','','N.E.','Valid',0,'Move r32 to debug register'),(722,'0F 23 /r','MOV','DR0-DR7','r64','','Valid','N.E',0,'Move r64 to extended debug\r\nregister.'),(723,'66 0F 28 /r','MOVAPD','xmm1','xmm2/m128','','Valid','Valid',0,'Move packed double-precision\r\nfloating-point values from\r\nxmm2/m128 to xmm1.'),(724,'66 0F 29 /r','MOVAPD','xmm2/m128','xmm1','','Valid','Valid',0,'Move packed double-precision\r\nfloating-point values from xmm1 to\r\nxmm2/m128.'),(725,'0F 28 /r','MOVAPS','xmm1','xmm2/m128','','Valid','Valid',0,'Move packed single-precision\r\nfloating-point values from\r\nxmm2/m128 to xmm1.'),(726,'0F 29 /r','MOVAPS','xmm2/m128','xmm1','','Valid','Valid',0,'Move packed single-precision\r\nfloating-point values from xmm1 to\r\nxmm2/m128.'),(727,'0F 6E /r','MOVD','mm','r/m32','','Valid','Valid',0,'Move doubleword from\r\nr/m32 to mm.'),(728,'REX.W + 0F 6E /r','MOVQ','mm','r/m64','','Valid','N.E.',0,'Move quadword from r/m64\r\nto mm.'),(729,'0F 7E /r','MOVD','r/m32','mm','','Valid','Valid',0,'Move doubleword from mm\r\nto r/m32.'),(730,'REX.W + 0F 7E /r','MOVQ','r/m64','mm','','Valid','N.E.',0,'Move quadword from mm to\r\nr/m64.'),(731,'66 0F 6E /r','MOVD','xmm','r/m32','','Valid','Valid',0,'Move doubleword from\r\nr/m32 to xmm.'),(732,'REX.W 66 0F 6E /r','MOVQ','xmm','r/m64','','Valid','N.E.',0,'Move quadword from r/m64\r\nto xmm.'),(733,'66 0F 7E /r','MOVD','r/m32','xmm','','Valid','Valid',0,'Move doubleword from\r\nxmm register to r/m32.'),(734,'REX.W 66 0F 7E /r','MOVQ','r/m64','xmm','','Valid','N.E.',0,'Move quadword from xmm\r\nregister to r/m64.'),(735,'F2 0F 12 /r','MOVDDUP','xmm1','xmm2/m64','','Valid','Valid',0,'Move one double-precision floatingpoint\r\nvalue from the lower 64-bit\r\noperand in xmm2/m64 to xmm1 and\r\nduplicate.'),(736,'66 0F 6F /r','MOVDQA','xmm1','xmm2/m128','','Valid','Valid',0,'Move aligned double quadword\r\nfrom xmm2/m128 to xmm1.'),(737,'66 0F 7F /r','MOVDQA','xmm2/m128','xmm1','','Valid','Valid',0,'Move aligned double quadword\r\nfrom xmm1 to xmm2/m128.'),(738,'F3 0F 6F /r','MOVDQU','xmm1','xmm2/m128','','Valid','Valid',0,'Move unaligned double\r\nquadword from xmm2/m128 to\r\nxmm1.'),(739,'F3 0F 7F /r','MOVDQU','xmm2/m128','xmm1','','Valid','Valid',0,'Move unaligned double\r\nquadword from xmm1 to\r\nxmm2/m128.'),(740,'F2 0F D6','MOVDQ2Q','mm','xmm','','Valid','Valid',0,'Move low quadword from\r\nxmm to mmx register.'),(741,'OF 12 /r','MOVHLPS','xmm1','xmm2','','Valid','Valid',0,'Move two packed singleprecision\r\nfloating-point values\r\nfrom high quadword of xmm2 to\r\nlow quadword of xmm1.'),(742,'66 0F 16 /r','MOVHPD','xmm','m64','','Valid','Valid',0,'Move double-precision floating-point\r\nvalue from m64 to high quadword of\r\nxmm.'),(743,'66 0F 17 /r','MOVHPD','m64','xmm','','Valid','Valid',0,'Move double-precision floating-point\r\nvalue from high quadword of xmm to\r\nm64.'),(744,'0F 16 /r','MOVHPS','xmm','m64','','Valid','Valid',0,'Move two packed single-precision\r\nfloating-point values from m64 to\r\nhigh quadword of xmm.'),(745,'0F 17 /r','MOVHPS','m64','xmm','','Valid','Valid',0,'Move two packed single-precision\r\nfloating-point values from high\r\nquadword of xmm to m64.'),(746,'OF 16 /r','MOVLHPS','xmm1','xmm2','','Valid','Valid',0,'Move two packed single-precision\r\nfloating-point values from low quadword\r\nof xmm2 to high quadword of xmm1.'),(747,'66 0F 12 /r','MOVLPD','xmm','m64','','Valid','Valid',0,'Move double-precision floating-point\r\nvalue from m64 to low quadword of xmm\r\nregister.'),(748,'66 0F 13 /r','MOVLPD','m64','xmm','','Valid','Valid',0,'Move double-precision floating-point\r\nnvalue from low quadword of xmm\r\nregister to m64.'),(749,'0F 12 /r','MOVLPS','xmm','m64','','Valid','Valid',0,'Move two packed single-precision\r\nfloating-point values from m64 to low\r\nquadword of xmm.'),(750,'0F 13 /r','MOVLPS','m64','xmm','','Valid','Valid',0,'Move two packed single-precision\r\nfloating-point values from low\r\nquadword of xmm to m64.'),(751,'66 0F 50 /r','MOVMSKPD','r32','xmm','','Valid','Valid',0,'Extract 2-bit sign mask\r\nfrom xmm and store in r32.'),(752,'66 REX.W 0F 50 /r','MOVMSKPD','r64','xmm','','Valid','N.E.',0,'Extract 2-bit sign mask\r\nfrom xmm and store in r64.\r\nZero extend 32-bit results\r\nto 64-bits.'),(753,'0F 50 /r','MOVMSKPS','r32','xmm','','Valid','Valid',0,'Extract 4-bit sign mask from xmm\r\nand store in r32.'),(754,'REX.W + 0F 50 /r','MOVMSKPS','r64','xmm','','Valid','N.E.',0,'Extract 4-bit sign mask from xmm\r\nand store in r64. Zero extend\r\n32-bit results to 64-bits.'),(755,'66 0F E7 /r','MOVNTDQ','m128','xmm','','Valid','Valid',0,'Move double quadword from xmm\r\nto m128 using non-temporal hint.'),(756,'0F C3 /r','MOVNTI','m32','r32','','Valid','Valid',0,'Move doubleword from r32 to\r\nm32 using non-temporal hint.'),(757,'REX.W + 0F C3 /r','MOVNTI','m64','r64','','Valid','N.E.',0,'Move quadword from r64 to\r\nm64 using non-temporal hint.'),(758,'66 0F 2B /r','MOVNTPD','m128','xmm','','Valid','Valid',0,'Move packed double-precision\r\nfloating-point values from xmm to\r\nm128 using non-temporal hint.'),(759,'0F 2B /r','MOVNTPS','m128','xmm','','Valid','Valid',0,'Move packed single-precision floatingpoint\r\nvalues from xmm to m128 using\r\nnon-temporal hint.'),(760,'0F E7 /r','MOVNTQ','m64','mm','','Valid','Valid',0,'Move quadword from mm to m64 using\r\nnon-temporal hint.'),(761,'0F 6F /r','MOVQ','mm','mm/m64','','Valid','Valid',0,'Move quadword from mm to\r\nmm/m64.'),(762,'F3 0F 7E','MOVQ','xmm1','xmm2/m64','','Valid','Valid',0,'Move quadword from\r\nxmm2/mem64 to xmm1.'),(763,'66 0F D6','MOVQ','xmm2/m64','xmm1','','Valid','Valid',0,'Move quadword from xmm1 to\r\nxmm2/mem64.'),(764,'F3 0F D6','MOVQ2DQ','xmm','mm','','Valid','Valid',0,'Move quadword from mmx to low\r\nquadword of xmm.'),(765,'A4','MOVS','m8','m8','','Valid','Valid',0,'For legacy mode, Move byte from\r\naddress DS:(E)SI to ES:(E)DI. For 64-bit\r\nmode move byte from address (R|E)SI\r\nto (R|E)DI.'),(766,'A5','MOVS','m16','m16','','Valid','Valid',0,'For legacy mode, move word from\r\naddress DS:(E)SI to ES:(E)DI. For 64-bit\r\nmode move word at address (R|E)SI to\r\n(R|E)DI.'),(767,'A5','MOVS','m32','m32','','Valid','Valid',0,'For legacy mode, move dword from\r\naddress DS:(E)SI to ES:(E)DI. For 64-bit\r\nmode move dword from address (R|E)SI\r\nto (R|E)DI.'),(768,'REX.W + A5','MOVS','m64','m64','','Valid','N.E.',0,'Move qword from address (R|E)SI to\r\n(R|E)DI.'),(769,'A4','MOVSB','','','','Valid','Valid',0,'For legacy mode, Move byte from\r\naddress DS:(E)SI to ES:(E)DI. For 64-bit\r\nmode move byte from address (R|E)SI\r\nto (R|E)DI.'),(770,'A5','MOVSW','','','','Valid','Valid',0,'For legacy mode, move word from\r\naddress DS:(E)SI to ES:(E)DI. For 64-bit\r\nmode move word at address (R|E)SI to\r\n(R|E)DI.'),(771,'A5','MOVSD','','','','Valid','Valid',0,'For legacy mode, move dword from\r\naddress DS:(E)SI to ES:(E)DI. For 64-bit\r\nmode move dword from address (R|E)SI\r\nto (R|E)DI.'),(772,'REX.W + A5','MOVSQ','','','','Valid','Valid',0,'Move qword from address (R|E)SI to\r\n(R|E)DI.'),(773,'F2 0F 10 /r','MOVSD','xmm1','xmm2/m64','','Valid','Valid',0,'Move scalar double-precision\r\nfloating-point value from\r\nxmm2/m64 to xmm1 register.'),(774,'F2 0F 11 /r','MOVSD','xmm2/m64','xmm1','','Valid','Valid',0,'Move scalar double-precision\r\nfloating-point value from xmm1\r\nregister to xmm2/m64.'),(775,'F3 0F 16 /r','MOVSHDUP','xmm1','xmm2/m128','','Valid','Valid',0,'Move two single-precision floatingpoint\r\nvalues from the higher 32-bit\r\noperand of each qword in\r\nxmm2/m128 to xmm1 and\r\nduplicate each 32-bit operand to the\r\nlower 32-bits of each qword.'),(776,'F3 0F 12 /r','MOVSLDUP','xmm1','xmm2/m128','','Valid','Valid',0,'Move two single-precision floating-point\r\nvalues from the lower 32-bit operand of\r\neach qword in xmm2/m128 to xmm1\r\nand duplicate each 32-bit operand to\r\nthe higher 32-bits of each qword.'),(777,'F3 0F 10 /r','MOVSS','xmm1','xmm2/m32','','Valid','Valid',0,'Move scalar single-precision\r\nfloating-point value from\r\nxmm2/m32 to xmm1 register.'),(778,'F3 0F 11 /r','MOVSS','xmm2/m32','xmm','','Valid','Valid',0,'Move scalar single-precision\r\nfloating-point value from xmm1\r\nregister to xmm2/m32.'),(779,'0F BE /r','MOVSX','r16','r/m8','','Valid','Valid',0,'Move byte to word with signextension.'),(780,'0F BE /r','MOVSX','r32','r/m8','','Valid','Valid',0,'Move byte to doubleword\r\nwith sign-extension.'),(781,'REX + 0F BE /r','MOVSX','r64','r/m8','','Valid','N.E.',0,'Move byte to quadword with\r\nsign-extension.'),(782,'0F BF /r','MOVSX','r32','r/m16','','Valid','Valid',0,'Move word to doubleword,\r\nwith sign-extension.'),(783,'REX.W + 0F BF /r','MOVSX','r64','r/m16','','Valid','N.E.',0,'Move word to quadword with\r\nsign-extension.'),(784,'REX.W + 63 /r','MOVSXD','r64','r/m32','','Valid','N.E.',0,'Move doubleword to'),(785,'66 0F 10 /r','MOVUPD','xmm1','xmm2/m128','','Valid','Valid',0,'Move packed double-precision\r\nfloating-point values from\r\nxmm2/m128 to xmm1.'),(786,'66 0F 11 /r','MOVUPD','xmm2/m128','xmm','','Valid','Valid',0,'Move packed double-precision\r\nfloating-point values from xmm1\r\nto xmm2/m128.'),(787,'0F 10 /r','MOVUPS','xmm1','xmm2/m128','','Valid','Valid',0,'Move packed single-precision floatingpoint\r\nvalues from xmm2/m128 to\r\nxmm1.'),(788,'0F 11 /r','MOVUPS','xmm2/m128','xmm1','','Valid','Valid',0,'Move packed single-precision floatingpoint'),(789,'0F B6 /r','MOVZX','r16','r/m8','','Valid','Valid',0,'Move byte to word with zeroextension.'),(790,'0F B6 /r','MOVZX','r32','r/m8','','Valid','Valid',0,'Move byte to doubleword,\r\nzero-extension.'),(791,'REX.W + 0F B6 /r','MOVZX','r64','r/m8','','Valid','N.E.',0,'Move byte to quadword, zeroextension.'),(792,'0F B7 /r','MOVZX','r32','r/m16','','Valid','Valid',0,'Move word to doubleword,\r\nzero-extension.'),(793,'REX.W + 0F B7 /r','MOVZX','r64','r/m16','','Valid','N.E.',0,'Move word to quadword, zeroextension.'),(794,'F6 /4','MUL','r/m8','','','Valid','Valid',0,'Unsigned multiply (AX ← AL ∗ r/m8).'),(795,'REX + F6 /4','MUL','r/m8','','','Valid','N.E.',0,'Unsigned multiply (AX ← AL ∗ r/m8).'),(796,'F7 /4','MUL','r/m16','','','Valid','Valid',0,'Unsigned multiply (DX:AX ← AX ∗\r\nr/m16).'),(797,'F7 /4','MUL','r/m32','','','Valid','Valid',0,'Unsigned multiply (EDX:EAX ← EAX ∗\r\nr/m32).'),(798,'REX.W + F7 /4','MUL','r/m64','','','Valid','N.E.',0,'Unsigned multiply (RDX:RAX ← RAX ∗\r\nr/m64.'),(799,'66 0F 59 /r','MULPD','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply packed double-precision\r\nfloating-point values in xmm2/m128 by\r\nxmm1.'),(800,'0F 59 /r','MULPS','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply packed single-precision\r\nfloating-point values in xmm2/mem by\r\nxmm1.'),(801,'F2 0F 59 /r','MULSD','xmm1','xmm2/m64','','Valid','Valid',0,'Multiply the low double-precision\r\nfloating-point value in xmm2/mem64\r\nby low double-precision floating-point\r\nvalue in xmm1.'),(802,'F3 0F 59 /r','MULS','xmm1','xmm2/m32','','Valid','Valid',0,'Multiply the low single-precision floatingpoint\r\nvalue in xmm2/mem by the low\r\nsingle-precision floating-point value in\r\nxmm1.'),(803,'OF 01 C9','MWAIT','','','','Valid','Valid',0,'A hint that allow the processor to stop\r\ninstruction execution and enter an\r\nimplementation-dependent optimized state\r\nuntil occurrence of a class of events.'),(804,'F6 /3','NEG','r/m8','','','Valid','Valid',0,'Two\'s complement negate r/m8.'),(805,'REX + F6 /3','NEG','r/m8','','','Valid','N.E.',0,'Two\'s complement negate r/m8.'),(806,'F7 /3','NEG','r/m16','','','Valid','Valid',0,'Two\'s complement negate\r\nr/m16.'),(807,'F7 /3','NEG','r/m32','','','Valid','Valid',0,'Two\'s complement negate\r\nr/m32.'),(808,'REX.W + F7 /3','NEG','r/m64','','','Valid','N.E.',0,'Two\'s complement negate\r\nr/m64.'),(809,'90','NOP','','','','Valid','Valid',0,'One byte no-operation instruction.'),(810,'0F 1F /0','NOP','r/m16','','','Valid','Valid',0,'Multi-byte no-operation instruction.'),(811,'0F 1F /0','NOP','r/m32','','','Valid','Valid',0,'Multi-byte no-operation instruction.'),(812,'F6 /2','NOT','r/m8','','','Valid','Valid',0,'Reverse each bit of r/m8.'),(813,'REX + F6 /2','NOT','r/m8','','','Valid','N.E.',0,'Reverse each bit of r/m8.'),(814,'F7 /2','NOT','r/m16','','','Valid','Valid',0,'Reverse each bit of r/m16.'),(815,'F7 /2','NOT','r/m32','','','Valid','Valid',0,'Reverse each bit of r/m32.'),(816,'REX.W + F7 /2','NOT','r/m64','','','Valid','N.E.',0,'Reverse each bit of r/m64.'),(817,'0C ib','OR','AL','imm8','','Valid','Valid',0,'AL OR imm8.'),(818,'0D iw','OR','AX','imm16','','Valid','Valid',0,'AX OR imm16.'),(819,'0D id','OR','EAX','imm32','','Valid','Valid',0,'EAX OR imm32.'),(820,'REX.W + 0D id','OR','RAX','imm32','','Valid','N.E.',0,'RAX OR imm32 (signextended).'),(821,'80 /1 ib','OR','r/m8','imm8','','Valid','Valid',0,'r/m8 OR imm8.'),(822,'REX + 80 /1 ib','OR','r/m8','imm8','','Valid','N.E.',0,'r/m8 OR imm8.'),(823,'81 /1 iw','OR','r/m16','imm16','','Valid','Valid',0,'r/m16 OR imm16.'),(824,'81 /1 id','OR','r/m32','mm32','','Valid','Valid',0,'r/m32 OR imm32.'),(825,'REX.W + 81 /1 id','OR','r/m64','imm32','','Valid','N.E',0,'r/m64 OR imm32 signextended).'),(826,'83 /1 ib','OR','r/m16','imm8','','Valid','Valid',0,'r/m16 OR imm8 (signextended).'),(827,'83 /1 ib','OR','r/m32','imm8','','Valid','Valid',0,'r/m32 OR imm8 (signextended).'),(828,'REX.W + 83 /1 ib','OR','r/m64','imm8','','Valid','N.E.',0,'r/m64 OR imm8 (signextended).'),(829,'08 /r','OR','r/m8','r8','','Valid','Valid',0,'r/m8 OR r8.'),(830,'REX + 08 /r','OR','r/m8','r8','','Valid','N.E.',0,'r/m8 OR r8.'),(831,'09 /r','OR','r/m16','r16','','Valid','Valid',0,'r/m16 OR r16.'),(832,'09 /r','OR','r/m32','r32','','Valid','Valid',0,'r/m32 OR r32.'),(833,'REX.W + 09 /r','OR','r/m64','r64','','Valid','N.E.',0,'r/m64 OR r64.'),(834,'0A /r','OR','r8','r/m8','','Valid','Valid',0,'r8 OR r/m8.'),(835,'REX + 0A /r','OR','r8','r/m8','','Valid','N.E.',0,'r8 OR r/m8.'),(836,'0B /r','OR','r16','r/m16','','Valid','Valid',0,'r16 OR r/m16.'),(837,'0B /r','OR','r32','r/m32','','Valid','Valid',0,'r32 OR r/m32.'),(838,'REX.W + 0B /r','OR','r64','r/m64','','Valid','N.E.',0,'r64 OR r/m64.'),(839,'66 0F 56 /r','ORPD','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise OR of xmm2/m128\r\nand xmm1.'),(840,'0F 56 /r','ORPS','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise OR of\r\nxmm2/m128 and\r\nxmm1.'),(841,'E6 ib','OUT','imm8','AL','','Valid','Valid',0,'Output byte in AL to I/O port\r\naddress imm8.'),(842,'E7 ib','OUT','imm8','AX','','Valid','Valid',0,'Output word in AX to I/O port'),(843,'E7 ib','OUT','imm8','EAX','','Valid','Valid',0,'Output doubleword in EAX to I/O\r\nport address imm8.'),(844,'EE','OUT','DX','AL','','Valid','Valid',0,'Output byte in AL to I/O port\r\naddress in DX.'),(845,'EF','OUT','DX','AX','','Valid','Valid',0,'Output word in AX to I/O port\r\naddress in DX.'),(846,'EF','OUT','DX','EAX','','Valid','Valid',0,'Output doubleword in EAX to I/O\r\nport address in DX.'),(847,'6E','OUTS','DX','m8','','Valid','Valid',0,'Output byte from memory\r\nlocation specified in DS:(E)SI or\r\nRSI to I/O port specified in DX'),(848,'6F','OUTS','DX','m16','','Valid','Valid',0,'Output word from memory\r\nlocation specified in DS:(E)SI or\r\nRSI to I/O port specified in DX'),(849,'6F','OUTS','DX','m32','','Valid','Valid',0,'Output doubleword from\r\nmemory location specified in\r\nDS:(E)SI or RSI to I/O port\r\nspecified in DX'),(850,'6E','OUTSB','','','','Valid','Valid',0,'Output byte from memory\r\nlocation specified in DS:(E)SI or\r\nRSI to I/O port specified in DX'),(851,'6F','OUTSW','','','','Valid','Valid',0,'Output word from memory\r\nlocation specified in DS:(E)SI or\r\nRSI to I/O port specified in DX'),(852,'6F','OUTSD','','','','Valid','Valid',0,'Output doubleword from\r\nmemory location specified in\r\nDS:(E)SI or RSI to I/O port\r\nspecified in DX'),(853,'0F 38 1C /r','PABSB','mm1','mm2/m64','','Valid','Valid',0,'Compute the absolute value of\r\nbytes in mm2/m64 and store\r\nUNSIGNED result in mm1.'),(854,'66 0F 38 1C /r','PABSB','xmm1','xmm2/m128','','Valid','Valid',0,'Compute the absolute value of\r\nbytes in xmm2/m128 and store\r\nUNSIGNED result in xmm1.'),(855,'0F 38 1D /r','PABSW','mm1','mm2/m64','','Valid','Valid',0,'Compute the absolute value of 16-\r\nbit integers in mm2/m64 and store\r\nUNSIGNED result in mm1.'),(856,'66 0F 38 1D /r','PABSW','xmm1','xmm2/m128','','Valid','Valid',0,'Compute the absolute value of 16-\r\nbit integers in xmm2/m128 and\r\nstore UNSIGNED result in xmm1.'),(857,'0F 38 1E /r','PABSD','mm1','mm2/m64','','Valid','Valid',0,'Compute the absolute value of 32-\r\nbit integers in mm2/m64 and store\r\nUNSIGNED result in mm1.'),(858,'66 0F 38 1E /r','PABSD','xmm1','xmm2/m128','','Valid','Valid',0,'Compute the absolute value of 32-\r\nbit integers in xmm2/m128 and\r\nstore UNSIGNED result in xmm1.'),(859,'0F 63 /r','PACKSSWB','mm1','mm2/m64','','Valid','Valid',0,'Converts 4 packed signed word\r\nintegers from mm1 and from\r\nmm2/m64 into 8 packed signed\r\nbyte integers in mm1 using signed\r\nsaturation.'),(860,'66 0F 63 /r','PACKSSWB','xmm1','xmm2/m128','','Valid','Valid',0,'Converts 8 packed signed word\r\nintegers from xmm1 and from\r\nxxm2/m128 into 16 packed signed\r\nbyte integers in xxm1 using signed\r\nsaturation.'),(861,'0F 6B /r','PACKSSDW','mm1','mm2/m64','','Valid','Valid',0,'Converts 2 packed signed\r\ndoubleword integers from mm1 and\r\nfrom mm2/m64 into 4 packed\r\nsigned word integers in mm1 using\r\nsigned saturation.'),(862,'66 0F 6B /r','PACKSSDW','xmm1','xmm2/m128','','Valid','Valid',0,'Converts 4 packed signed\r\ndoubleword integers from xmm1\r\nand from xxm2/m128 into 8 packed\r\nsigned word integers in xxm1 using\r\nsigned saturation.'),(863,'0F 67 /r','PACKUSWB','mm','mm/m64','','Valid','Valid',0,'Converts 4 signed word integers\r\nfrom mm and 4 signed word\r\nintegers from mm/m64 into 8\r\nunsigned byte integers in mm using\r\nunsigned saturation.'),(864,'66 0F 67 /r','PACKUSWB','xmm1','xmm2/m128','','Valid','Valid',0,'Converts 8 signed word integers\r\nfrom xmm1 and 8 signed word\r\nintegers from xmm2/m128 into 16\r\nunsigned byte integers in xmm1\r\nusing unsigned saturation.'),(865,'0F FC /r','PADDB','mm','mm/m64','','Valid','Valid',0,'Add packed byte integers from\r\nmm/m64 and mm.'),(866,'66 0F FC /r','PADDB','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed byte integers from\r\nxmm2/m128 and xmm1.'),(867,'0F FD /r','PADDW','mm','mm/m64','','Valid','Valid',0,'Add packed word integers from\r\nmm/m64 and mm.'),(868,'66 0F FD /r','PADDW','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed word integers from\r\nxmm2/m128 and xmm1.'),(869,'0F FE /r','PADDD','mm','mm/m64','','Valid','Valid',0,'Add packed doubleword integers from\r\nmm/m64 and mm.'),(870,'66 0F FE /r','PADDD','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed doubleword integers from\r\nxmm2/m128 and xmm1.'),(871,'0F D4 /r','PADDQ','mm1','mm2/m64','','Valid','Valid',0,'Add quadword integer\r\nmm2/m64 to mm1.'),(872,'66 0F D4 /r','PADDQ','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed quadword integers\r\nxmm2/m128 to xmm1.'),(873,'0F EC /r','PADDSB','mm','mm/m64','','Valid','Valid',0,'Add packed signed byte integers\r\nfrom mm/m64 and mm and\r\nsaturate the results.'),(874,'66 0F EC /r','PADDSB','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed signed byte integers\r\nfrom xmm2/m128 and xmm1\r\nsaturate the results.'),(875,'0F ED /r','PADDSW','mm','mm/m64','','Valid','Valid',0,'Add packed signed word integers\r\nfrom mm/m64 and mm and\r\nsaturate the results.'),(876,'66 0F ED /r','PADDSW','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed signed word integers\r\nfrom xmm2/m128 and xmm1\r\nand saturate the results.'),(877,'0F DC /r','PADDUSB','mm','mm/m64','','Valid','Valid',0,'Add packed unsigned byte integers\r\nfrom mm/m64 and mm and\r\nsaturate the results.'),(878,'66 0F DC /r','PADDUSB','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed unsigned byte integers\r\nfrom xmm2/m128 and xmm1\r\nsaturate the results.'),(879,'0F DD /r','PADDUSW','mm','mm/m64','','Valid','Valid',0,'Add packed unsigned word\r\nintegers from mm/m64 and mm\r\nand saturate the results.'),(880,'66 0F DD /r','PADDUSW','xmm1','xmm2/m128','','Valid','Valid',0,'Add packed unsigned word\r\nintegers from xmm2/m128 to\r\nxmm1 and saturate the results.'),(881,'0F 3A 0F','PALIGNR','mm1','mm2/m64','imm8','Valid','Valid',0,'Concatenate destination and source\r\noperands, extract byte-aligned\r\nresult shifted to the right by\r\nconstant into mm1.'),(882,'66 0F 3A 0F','PALIGNR','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Concatenate destination and source\r\noperands, extract byte-aligned\r\nresult shifted to the right by\r\nconstant into xmm1'),(883,'0F DB /r','PAND','mm','mm/m64','','Valid','Valid',0,'Bitwise AND mm/m64 and\r\nmm.'),(884,'66 0F DB /r','PAND','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise AND of\r\nxmm2/m128 and xmm1.'),(885,'0F DF /r','PANDN','mm','mm/m64','','Valid','Valid',0,'Bitwise AND NOT of\r\nmm/m64 and mm.'),(886,'66 0F DF /r','PANDN','xmm1','xmm2/m128','','Valid','Valid',0,'ValidBitwise AND NOT of\r\nxmm2/m128 and\r\nxmm1.'),(887,'F3 90','PAUSE','','','','Valid','Valid',0,'Gives hint to processor that improves\r\nperformance of spin-wait loops.'),(888,'0F E0 /r','PAVGB','mm1','mm2/m64','','Valid','Valid',0,'Average packed unsigned byte\r\nintegers from mm2/m64 and mm1\r\nwith rounding.'),(889,'66 0F E0 /r','PAVGB','xmm1','xmm2/m128','','Valid','Valid',0,'Average packed unsigned byte. (Previously was 66 0F E0, /r ; removed comma suggestive of typo)'),(890,'0F E3 /r','PAVGW','mm1','mm2/m64','','Valid','Valid',0,'Average packed unsigned word\r\nintegers from mm2/m64 and mm1\r\nwith rounding.'),(891,'66 0F E3 /r','PAVGW','xmm1','xmm2/m128','','Valid','Valid',0,'Average packed unsigned word\r\nintegers from xmm2/m128 and xmm1\r\nwith rounding.'),(892,'0F 74 /r','PCMPEQB','mm','mm/m64','','Valid','Valid',0,'Compare packed bytes in\r\nmm/m64 and mm for equality.'),(893,'66 0F 74 /r','PCMPEQB','xmm1','xmm2/m128','','Valid','Valid',0,'Compare packed bytes in\r\nxmm2/m128 and xmm1 for\r\nequality.'),(894,'0F 75 /r','PCMPEQW','mm','mm/m64','','Valid','Valid',0,'Compare packed words in\r\nmm/m64 and mm for equality.'),(895,'66 0F 75 /r','PCMPEQW','xmm1','xmm2/m128','','Valid','Valid',0,'Compare packed words in\r\nxmm2/m128 and xmm1 for\r\nequality.'),(896,'0F 76 /r','PCMPEQD','mm','mm/m64','','Valid','Valid',0,'Compare packed doublewords in\r\nmm/m64 and mm for equality.'),(897,'66 0F 76 /r','PCMPEQD','xmm1','xmm2/m128','','Valid','Valid',0,'Compare packed doublewords in\r\nxmm2/m128 and xmm1 for\r\nequality.'),(898,'0F 64 /r','PCMPGTB','mm','mm/m64','','Valid','Valid',0,'Compare packed signed byte'),(899,'66 0F 64 /r','PCMPGTB','xmm1','xmm2/m128','','Valid','Valid',0,'Compare packed signed byte\r\nintegers in xmm1 and\r\nxmm2/m128 for greater than.'),(900,'0F 65 /r','PCMPGTW','mm','mm/m64','','Valid','Valid',0,'Compare packed signed word\r\nintegers in mm and mm/m64 for\r\ngreater than.'),(901,'66 0F 65 /r','PCMPGTW','xmm1','xmm2/m128','','Valid','Valid',0,'Compare packed signed word\r\nintegers in xmm1 and\r\nxmm2/m128 for greater than.'),(902,'0F 66 /r','PCMPGTD','mm','mm/m64','','Valid','Valid',0,'Compare packed signed\r\ndoubleword integers in mm and\r\nmm/m64 for greater than.'),(903,'66 0F 66 /r','PCMPGTD','xmm1','xmm2/m128','','Valid','Valid',0,'Compare packed signed\r\ndoubleword integers in xmm1\r\nand xmm2/m128 for greater\r\nthan.'),(904,'0F C5 /r ib','PEXTRW','r32','mm','imm8','Valid','Valid',0,'Extract the word specified by\r\nimm8 from mm and move it to\r\nr32, bits 15-0. Zero-extend the\r\nresult.'),(905,'REX.W + 0F C5 /r ib','PEXTRW','r64','mm','imm8','Valid','N.E.',0,'Extract the word specified by\r\nimm8 from mm and move it to\r\nr64, bits 15-0. Zero-extend the\r\nresult.'),(906,'66 0F C5 /r ib','PEXTRW','r32','xmm','imm8','Valid','Valid',0,'Extract the word specified by\r\nimm8 from xmm and move it to\r\nr32, bits 15-0. Zero-extend the\r\nresult.'),(907,'66 REX.W 0F C5 /r ib','PEXTRW','r64','xmm','imm8','Valid','N.E.',0,'Extract the word specified by\r\nimm8 from xmm and move it to\r\nr64, bits 15-0. Zero-extend the\r\nresult.'),(908,'0F 38 01 /r','PHADDW','mm1','mm2/m64','','Valid','Valid',0,'Add 16-bit signed integers\r\nhorizontally, pack to MM1.'),(909,'66 0F 38 01 /r','PHADDW','xmm1','xmm2/m128','','Valid','Valid',0,'Add 16-bit signed integers\r\nhorizontally, pack to XMM1.'),(910,'0F 38 02 /r','PHADDD','mm1','mm2/m64','','Valid','Valid',0,'Add 32-bit signed integers\r\nhorizontally, pack to MM1.'),(911,'66 0F 38 02 /r','PHADDD','xmm1','xmm2/m128','','Valid','Valid',0,'Add 32-bit signed integers\r\nhorizontally, pack to XMM1.'),(912,'0F 38 03 /r','PHADDSW','mm1','mm2/m64','','Valid','Valid',0,'Add 16-bit signed integers\r\nhorizontally, pack saturated integers\r\nto MM1.'),(913,'66 0F 38 03 /r','PHADDSW','xmm1','xmm2/m128','','Valid','Valid',0,'Add 16-bit signed integers\r\nhorizontally, pack saturated integers\r\nto XMM1.'),(914,'0F 38 05 /r','PHSUBW','mm1','mm2/m64','','Valid','Valid',0,'Subtract 16-bit signed\r\nintegers horizontally, pack\r\nto MM1.'),(915,'66 0F 38 05 /r','PHSUBW','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract 16-bit signed\r\nintegers horizontally, pack\r\nto XMM1.'),(916,'0F 38 06 /r','PHSUBD','mm1','mm2/m64','','Valid','Valid',0,'Subtract 32-bit signed\r\nintegers horizontally, pack\r\nto MM1.'),(917,'66 0F 38 06 /r','PHSUBD','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract 32-bit signed'),(918,'0F 38 07 /r','PHSUBSW','mm1','mm2/m64','','Valid','Validc',0,'Subtract 16-bit signed\r\ninteger horizontally, pack\r\nsaturated integers to MM1.'),(919,'66 0F 38 07 /r','PHSUBSW','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract 16-bit signed\r\ninteger horizontally, pack\r\nsaturated integers to\r\nXMM1'),(920,'0F C4 /r ib','PINSRW','mm','r32/m16','imm8','Valid','Valid',0,'Insert the low word from\r\nr32 or from m16 into mm\r\nat the word position\r\nspecified by imm8'),(921,'REX.W + 0F C4 /r ib','PINSRW','mm','r64/m16','imm8','Valid','N.E.',0,'Insert the low word from\r\nr64 or from m16 into mm\r\nat the word position\r\nspecified by imm8'),(922,'66 0F C4 /r ib','PINSRW','xmm','r32/m16','imm8','Valid','Valid',0,'Move the low word of r32\r\nor from m16 into xmm at\r\nthe word position specified\r\nby imm8.'),(923,'66 REX.W 0F C4 /r ib','PINSRW','xmm','r64/m16','imm8','Valid','N.E.',0,'Move the low word of r64\r\nor from m16 into xmm at\r\nthe word position specified\r\nby imm8.'),(924,'0F 38 04 /r','PMADDUBSW','mm1','mm2/m64','','Valid','Valid',0,'Multiply signed and\r\nunsigned bytes, add\r\nhorizontal pair of signed\r\nwords, pack saturated\r\nsigned-words to MM1.'),(925,'66 0F 38 04 /r','PMADDUBSW','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply signed and\r\nunsigned bytes, add\r\nhorizontal pair of signed\r\nwords, pack saturated\r\nsigned-words to XMM1.'),(926,'0F F5 /r','PMADDWD','mm','mm/m64','','Valid','Valid',0,'Multiply the packed words in mm\r\nby the packed words in mm/m64,\r\nadd adjacent doubleword results,\r\nand store in mm.'),(927,'66 0F F5 /r','PMADDWD','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply the packed word integers\r\nin xmm1 by the packed word\r\nintegers in xmm2/m128, add\r\nadjacent doubleword results, and\r\nstore in xmm1.'),(928,'0F EE /r','PMAXSW','mm1','mm2/m64','','Valid','Valid',0,'Compare signed word integers in\r\nmm2/m64 and mm1 and return\r\nmaximum values.'),(929,'66 0F EE /r','PMAXSW','xmm1','xmm2/m128','','Valid','Valid',0,'Compare signed word integers in\r\nxmm2/m128 and xmm1 and return\r\nmaximum values.'),(930,'0F DE /r','PMAXUB','mm1','mm2/m64','','Valid','Valid',0,'Compare unsigned byte integers\r\nin mm2/m64 and mm1 and\r\nreturns maximum values.'),(931,'66 0F DE /r','PMAXUB','xmm1','xmm2/m128','','Valid','Valid',0,'Compare unsigned byte integers\r\nin xmm2/m128 and xmm1 and\r\nreturns maximum values.'),(932,'0F EA /r','PMINSW','mm1','mm2/m64','','Valid','Valid',0,'Compare signed word integers in\r\nmm2/m64 and mm1 and return\r\nminimum values.'),(933,'66 0F EA /r','PMINSW','xmm1','xmm2/m128','','Valid','Valid',0,'Compare signed word integers in\r\nxmm2/m128 and xmm1 and return\r\nminimum values.'),(934,'0F DA /r','PMINUB','mm1','mm2/m64','','Valid','Valid',0,'Compare unsigned byte integers in\r\nmm2/m64 and mm1 and returns\r\nminimum values.'),(935,'66 0F DA /r','PMINUB','xmm1','xmm2/m128','','Valid','Valid',0,'Compare unsigned byte integers in\r\nxmm2/m128 and xmm1 and\r\nreturns minimum values.'),(936,'0F D7 /r','PMOVMSKB','r32','mm','','Valid','Valid',0,'Move a byte mask of mm to\r\nr32.'),(937,'REX.W + 0F D7 /r','PMOVMSKB','r64','mm','','Valid','N.E.',0,'Move a byte mask of mm to\r\nthe lower 32-bits of r64 and\r\nzero-fill the upper 32-bits.'),(938,'66 0F D7 /r','PMOVMSKB','r32','xmm','','Valid','Valid',0,'Move a byte mask of xmm\r\nto r32.'),(939,'66 REX.W 0F D7 /r','PMOVMSKB','r64','xmm','','Valid','N.E.',0,'Move a byte mask of xmm\r\nto the lower 32-bits of r64\r\nand zero-fill the upper\r\n32-bits.'),(940,'0F 38 0B /r','PMULHRSW','mm1','mm2/m64','','Valid','Valid',0,'Multiply 16-bit signed\r\nwords, scale and round\r\nsigned doublewords, pack\r\nhigh 16 bits to MM1.'),(941,'66 0F 38 0B /r','PMULHRSW','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply 16-bit signed\r\nwords, scale and round\r\nsigned doublewords, pack\r\nhigh 16 bits to XMM1.'),(942,'0F E4 /r','PMULHUW','mm1','mm2/m64','','Valid','Valid',0,'Multiply the packed unsigned\r\nword integers in mm1 register\r\nand mm2/m64, and store the\r\nhigh 16 bits of the results in\r\nmm1.'),(943,'66 0F E4 /r','PMULHUW','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply the packed unsigned\r\nword integers in xmm1 and\r\nxmm2/m128, and store the high\r\n16 bits of the results in xmm1'),(944,'0F E5 /r','PMULHW','mm','mm/m64','','Valid','Valid',0,'Multiply the packed signed word\r\nintegers in mm1 register and\r\nmm2/m64, and store the high 16\r\nbits of the results in mm1.'),(945,'66 0F E5 /r','PMULHW','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply the packed signed word\r\nintegers in xmm1 and\r\nxmm2/m128, and store the high 16\r\nbits of the results in xmm1.'),(946,'0F D5 /r','PMULLW','mm','mm/m64','','Valid','Valid',0,'Multiply the packed signed word\r\nintegers in mm1 register and\r\nmm2/m64, and store the low 16\r\nbits of the results in mm1.'),(947,'66 0F D5 /r','PMULLW','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply the packed signed word\r\nintegers in xmm1 and xmm2/m128,\r\nand store the low 16 bits of the\r\nresults in xmm1.'),(948,'0F F4 /r','PMULUDQ','mm1','mm2/m64','','Valid','Valid',0,'Multiply unsigned doubleword\r\ninteger in mm1 by unsigned\r\ndoubleword integer in mm2/m64,\r\nand store the quadword result in\r\nmm1.'),(949,'66 OF F4 /r','PMULUDQ','xmm1','xmm2/m128','','Valid','Valid',0,'Multiply packed unsigned\r\ndoubleword integers in xmm1 by\r\npacked unsigned doubleword\r\nintegers in xmm2/m128, and store\r\nthe quadword results in xmm1.'),(950,'8F /0','POP','r/m16','','','Valid','Valid',0,'Pop top of stack into m16; increment stack\r\npointer.'),(951,'8F /0','POP','r/m32','','','N.E.','Valid',0,'Pop top of stack into m32; increment stack\r\npointer.'),(952,'8F /0','POP','r/m64','','','Valid','N.E.',0,'Pop top of stack into m64; increment stack\r\npointer. Cannot encode 32-bit operand size.'),(953,'58+ rw','POP','r16','','','Valid','Valid',0,'Pop top of stack into r16; increment stack\r\npointer.'),(954,'58+ rd','POP','r32','','','N.E.','Valid',0,'Pop top of stack into r32; increment stack\r\npointer.'),(955,'58+ rd','POP','r64','','','Valid','N.E.',0,'Pop top of stack into r64; increment stack\r\npointer. Cannot encode 32-bit operand size.'),(956,'1F','POP DS','','','','Invalid','Valid',0,'Pop top of stack into DS; increment stack\r\npointer.'),(957,'07','POP','ES','','','Invalid','Valid',0,'Pop top of stack into ES; increment stack\r\npointer.'),(958,'17','POP','SS','','','Invalid','Valid',0,'Pop top of stack into SS; increment stack\r\npointer.'),(959,'0F A1','POP','FS','','','Valid','Valid',0,'Pop top of stack into FS; increment stack\r\npointer by 16 bits.'),(960,'0F A1','POP','FS','','','N.E.','Valid',0,'Pop top of stack into FS; increment stack\r\npointer by 32 bits.'),(961,'0F A1','POP','FS','','','Valid','N.E.',0,'Pop top of stack into FS; increment stack\r\npointer by 64 bits.'),(962,'0F A9','POP','GS','','','Valid','Valid',0,'Pop top of stack into GS; increment stack\r\npointer by 16 bits.'),(963,'0F A9','POP','GS','','','N.E.','Valid',0,'Pop top of stack into GS; increment stack\r\npointer by 32 bits.'),(964,'0F A9','POP','GS','','','Valid','N.E.',0,'Pop top of stack into GS; increment stack\r\npointer by 64 bits.'),(965,'61','POPA','','','','Invalid','Valid',0,'Pop DI, SI, BP, BX, DX, CX, and AX.'),(966,'61','POPAD','','','','Invalid','Valid',0,'Pop EDI, ESI, EBP, EBX, EDX, ECX, and\r\nEAX.'),(967,'9D','POPF','','','','Valid','Valid',0,'Pop top of stack into lower 16 bits of\r\nEFLAGS.'),(968,'REX.W + 9D','POPFQ','','','','Valid','N.E.',0,'Pop top of stack and zero-extend into\r\nRFLAGS.'),(969,'0F EB /r','POR','mm','mm/m64','','Valid','Valid',0,'Bitwise OR of mm/m64 and mm.'),(970,'66 0F EB /r','POR','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise OR of xmm2/m128 and\r\nxmm1.'),(971,'0F 18 /1','PREFETCHT0','m8','','','Valid','Valid',0,'Move data from m8 closer to the\r\nprocessor using T0 hint.'),(972,'0F 18 /2','PREFETCHT1','m8','','','Valid','Valid',0,'Move data from m8 closer to the\r\nprocessor using T1 hint.'),(973,'0F 18 /3','PREFETCHT2','m8','','','Valid','Valid',0,'Move data from m8 closer to the\r\nprocessor using T2 hint.'),(974,'0F 18 /0','PREFETCHNTA','m8','','','Valid','Valid',0,'Move data from m8 closer to the\r\nprocessor using NTA hint.'),(975,'0F F6 /r','PSADBW','mm1','mm2/m64','','Valid','Valid',0,'Computes the absolute differences of\r\nthe packed unsigned byte integers\r\nfrom mm2 /m64 and mm1; differences\r\nare then summed to produce an\r\nunsigned word integer result.'),(976,'66 0F F6 /r','PSADBW','xmm1','xmm2/m128','','Valid','Valid',0,'Computes the absolute differences of\r\nthe packed unsigned byte integers\r\nfrom xmm2 /m128 and xmm1; the 8\r\nlow differences and 8 high differences\r\nare then summed separately to\r\nproduce two unsigned word integer\r\nresults.'),(977,'0F 38 00 /r','PSHUFB','mm1','mm2/m64','','Valid','Valid',0,'Shuffle bytes in mm1\r\naccording to contents of\r\nmm2/m64.'),(978,'66 0F 38 00 /r','PSHUFB','xmm1','xmm2/m128','','Valid','Valid',0,'Shuffle bytes in xmm1\r\naccording to contents of\r\nxmm2/m128.'),(979,'66 0F 70 /r ib','PSHUFD','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Shuffle the doublewords in\r\nxmm2/m128 based on the\r\nencoding in imm8 and store\r\nthe result in xmm1.'),(980,'F3 0F 70 /r ib','PSHUFHW','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Shuffle the high words in\r\nxmm2/m128 based on the\r\nencoding in imm8 and store\r\nthe result in xmm1.'),(981,'F2 0F 70 /r ib','PSHUFLW','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Shuffle the low words in\r\nxmm2/m128 based on the\r\nencoding in imm8 and store the\r\nresult in xmm1.'),(982,'0F 70 /r ib','PSHUFW','mm1','mm2/m64','imm8','Valid','Valid',0,'Shuffle the words in mm2/m64\r\nbased on the encoding in imm8 and\r\nstore the result in mm1.'),(983,'0F 38 08 /r','PSIGNB','mm1','mm2/m64','','Valid','Valid',0,'Negate packed byte integers in mm1\r\nif the corresponding sign in mm2/m64\r\nis less than zero.'),(984,'66 0F 38 08 /r','PSIGNB','xmm1','xmm2/m128','','Valid','Valid',0,'Negate packed byte integers in xmm1\r\nif the corresponding sign in\r\nxmm2/m128 is less than zero.'),(985,'0F 38 09 /r','PSIGNW','mm1','mm2/m6','','Valid','Valid',0,'Negate packed 16-bit integers in mm1\r\nif the corresponding sign in mm2/m64\r\nis less than zero.'),(986,'66 0F 38 09 /r','PSIGNW','xmm1','xmm2/m128','','Valid','Valid',0,'Negate packed 16-bit integers in\r\nxmm1 if the corresponding sign in\r\nxmm2/m128 is less than zero.'),(987,'0F 38 0A /r','PSIGND','mm1','mm2/m64','','Valid','Valid',0,'Negate packed doubleword integers in'),(988,'66 0F 38 0A /r','PSIGND','xmm1','xmm2/m128','','Valid','Valid',0,'Negate packed doubleword integers in\r\nxmm1 if the corresponding sign in\r\nxmm2/m128 is less than zero.'),(989,'66 0F 73 /7 ib','PSLLDQ','xmm1','imm8','','Valid','Valid',0,'Shift xmm1 left by imm8 bytes\r\nwhile shifting in 0s.'),(990,'0F F1 /r','PSLLW','mm','mm/m64','','Valid','Valid',0,'Shift words in mm left mm/m64\r\nwhile shifting in 0s.'),(991,'66 0F F1 /r','PSLLW','xmm1','xmm2/m128','','Valid','Valid',0,'Shift words in xmm1 left by\r\nxmm2/m128 while shifting in 0s.'),(992,'0F 71 /6 ib','PSLLW','xmm1','imm8','','Valid','Valid',0,'Shift words in mm left by imm8\r\nwhile shifting in 0s.'),(993,'66 0F 71 /6 ib','PSLLW','xmm1','imm8','','Valid','Valid',0,'Shift words in xmm1 left by\r\nimm8 while shifting in 0s.'),(994,'0F F2 /r','PSLLD','mm','mm/m64','','Valid','Valid',0,'Shift doublewords in mm left by\r\nmm/m64 while shifting in 0s.'),(995,'66 0F F2 /r','PSLLD','xmm1','xmm2/m128','','Valid','Valid',0,'Shift doublewords in xmm1 left\r\nby xmm2/m128 while shifting in\r\n0s.'),(996,'0F 72 /6 ib','PSLLD','mm','imm8','','Valid','Valid',0,'Shift doublewords in mm left by\r\nimm8 while shifting in 0s.'),(997,'66 0F 72 /6 ib','PSLLD','xmm1','imm8','','Valid','Valid',0,'Shift doublewords in xmm1 left\r\nby imm8 while shifting in 0s.'),(998,'0F F3 /r','PSLLQ','mm','mm/m64','','Valid','Valid',0,'Shift quadword in mm left by\r\nmm/m64 while shifting in 0s.'),(999,'66 0F F3 /r','PSLLQ','xmm1','xmm2/m128','','Valid','Valid',0,'Shift quadwords in xmm1 left by\r\nxmm2/m128 while shifting in 0s.'),(1000,'0F 73 /6 ib','PSLLQ','mm','imm8','','Valid','Valid',0,'Shift quadword in mm left by\r\nimm8 while shifting in 0s.'),(1001,'66 0F 73 /6 ib','PSLLQ','xmm1','imm8','','Valid','Valid',0,'Shift quadwords in xmm1 left by\r\nimm8 while shifting in 0s.'),(1002,'0F E1 /r','PSRAW','mm','mm/m64','','Valid','Valid',0,'Shift words in mm right by\r\nmm/m64 while shifting in sign\r\nbits.'),(1003,'66 0F E1 /r','PSRAW','xmm1','xmm2/m128','','Valid','Valid',0,'Shift words in xmm1 right by\r\nxmm2/m128 while shifting in sign\r\nbits.'),(1004,'0F 71 /4 ib','PSRAW','mm','imm8','','Valid','Valid',0,'Shift words in mm right by imm8\r\nwhile shifting in sign bits'),(1005,'66 0F 71 /4 ib','PSRAW','xmm1','imm8','','Valid','Valid',0,'Shift words in xmm1 right by\r\nimm8 while shifting in sign bits'),(1006,'0F E2 /r','PSRAD','mm','mm/m64','','Valid','Valid',0,'Shift doublewords in mm right by\r\nmm/m64 while shifting in sign\r\nbits.'),(1007,'66 0F E2 /r','PSRAD','xmm1','xmm2/m128','','Valid','Valid',0,'Shift doubleword in xmm1 right\r\nby xmm2 /m128 while shifting in\r\nsign bits.'),(1008,'0F 72 /4 ib','PSRAD','mm','imm8','','Valid','Valid',0,'Shift doublewords in mm right by\r\nimm8 while shifting in sign bits.'),(1009,'66 0F 72 /4 ib','PSRAD','xmm1','imm8','','Valid','Valid',0,'Shift doublewords in xmm1 right\r\nby imm8 while shifting in sign bits.'),(1010,'66 0F 73 /3 ib','PSRLDQ','imm8','','','Valid','Valid',0,'Shift xmm1 right by imm8 while\r\nshifting in 0s.'),(1011,'0F D1 /r','PSRLW','mm','mm/m64','','Valid','Valid',0,'Shift words in mm right by amount\r\nspecified in mm/m64 while shifting in\r\n0s.'),(1012,'66 0F D1 /r','PSRLW','xmm1','xmm2/m128','','Valid','Valid',0,'Shift words in xmm1 right by amount\r\nspecified in xmm2/m128 while\r\nshifting in 0s.'),(1013,'0F 71 /2 ib','PSRLW','mm','imm8','','Valid','Valid',0,'Shift words in mm right by imm8 while\r\nshifting in 0s.'),(1014,'66 0F 71 /2 ib','PSRLW','xmm1','imm8','','Valid','Valid',0,'Shift words in xmm1 right by imm8\r\nwhile shifting in 0s.'),(1015,'0F D2 /r','PSRLD','mm','mm/m64','','Valid','Valid',0,'Shift doublewords in mm right by\r\namount specified in mm/m64 while\r\nshifting in 0s.'),(1016,'66 0F D2 /r','PSRLD','xmm1','xmm2/m128','','Valid','Valid',0,'Shift doublewords in xmm1 right by\r\namount specified in xmm2 /m128\r\nwhile shifting in 0s.'),(1017,'0F 72 /2 ib','PSRLD','mm','imm8','','Valid','Valid',0,'Shift doublewords in mm right by\r\nimm8 while shifting in 0s.'),(1018,'66 0F 72 /2 ib','PSRLD','xmm1','imm8','','Valid','Valid',0,'Shift doublewords in xmm1 right by\r\nimm8 while shifting in 0s.'),(1019,'0F D3 /r','PSRLQ','xmm1','xmm2/m128','','Valid','Valid',0,'Shift quadwords in xmm1 right by\r\namount specified in xmm2/m128\r\nwhile shifting in 0s.'),(1020,'0F 73 /2 ib','PSRLQ','mm','imm8','','Valid','Valid',0,'Shift mm right by imm8 while shifting\r\nin 0s.'),(1021,'66 0F 73 /2 ib','PSRLQ','xmm1','imm8','','Valid','Valid',0,'Shift quadwords in xmm1 right by\r\nimm8 while shifting in 0s.'),(1022,'0F F8 /r','PSUBB','mm','mm/m64','','Valid','Valid',0,'Subtract packed byte integers in\r\nmm/m64 from packed byte integers in\r\nmm.'),(1023,'66 0F F8 /','PSUBB','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed byte integers in\r\nxmm2/m128 from packed byte\r\nintegers in xmm1.'),(1024,'0F F9 /r','PSUBW','mm','mm/m64','','Valid','Valid',0,'Subtract packed word integers in\r\nmm/m64 from packed word integers in\r\nmm.'),(1025,'66 0F F9 /r','PSUBW','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed word integers in\r\nxmm2/m128 from packed word\r\nintegers in xmm1.'),(1026,'0F FA /r','PSUBD','mm','mm/m64','','Valid','Valid',0,'Subtract packed doubleword integers\r\nin mm/m64 from packed doubleword\r\nintegers in mm.'),(1027,'66 0F FA /r','PSUBD','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed doubleword integers\r\nin xmm2/mem128 from packed\r\ndoubleword integers in xmm1.'),(1028,'0F FB /r','PSUBQ','mm1','mm2/m64','','Valid','Valid',0,'Subtract quadword integer\r\nin mm1 from mm2 /m64.'),(1029,'66 0F FB /r','PSUBQ','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed quadword\r\nintegers in xmm1 from\r\nxmm2 /m128.'),(1030,'0F E8 /r','PSUBSB','mm','mm/m64','','Valid','Valid',0,'Subtract signed packed bytes in\r\nmm/m64 from signed packed bytes\r\nin mm and saturate results.'),(1031,'66 0F E8 /r','PSUBSB','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed signed byte\r\nintegers in xmm2/m128 from\r\npacked signed byte integers in\r\nxmm1 and saturate results.'),(1032,'0F E9 /r','PSUBSW','mm','mm/m64','','Valid','Valid',0,'Subtract signed packed words in\r\nmm/m64 from signed packed words\r\nin mm and saturate results.'),(1033,'66 0F E9 /r','PSUBSW','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed signed word\r\nintegers in xmm2/m128 from\r\npacked signed word integers in\r\nxmm1 and saturate results.'),(1034,'0F D8 /r','PSUBUSB','mm','mm/m64','','Valid','Valid',0,'Subtract unsigned packed bytes in\r\nmm/m64 from unsigned packed\r\nbytes in mm and saturate result.'),(1035,'66 0F D8 /r','PSUBUSB','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed unsigned byte\r\nintegers in xmm2/m128 from packed\r\nunsigned byte integers in xmm1 and\r\nsaturate result.'),(1036,'0F D9 /r','PSUBUSW','mm','mm/m64','','Valid','Valid',0,'Subtract unsigned packed words in\r\nmm/m64 from unsigned packed\r\nwords in mm and saturate result.'),(1037,'66 0F D9 /r','PSUBUSW','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed unsigned word\r\nintegers in xmm2/m128 from packed\r\nunsigned word integers in xmm1 and\r\nsaturate result.'),(1038,'0F 68 /r','PUNPCKHBW','mm','mm/m64','','Valid','Valid',0,'Unpack and interleave high-order\r\nbytes from mm and mm/m64\r\ninto mm.'),(1039,'66 0F 68 /r','PUNPCKHBW','xmm1','xmm2/m128','','Valid','Valid',0,'Unpack and interleave high-order\r\nbytes from xmm1 and\r\nxmm2/m128 into xmm1.'),(1040,'0F 69 /r','PUNPCKHWD','mm','mm/m64','','Valid','Valid',0,'Unpack and interleave high-order\r\nwords from mm and mm/m64\r\ninto mm.'),(1041,'66 0F 69 /r','PUNPCKHWD','xmm1','xmm2/m128','','Valid','Valid',0,'Unpack and interleave high-order\r\nwords from xmm1 and\r\nxmm2/m128 into xmm1.'),(1042,'0F 6A /r','PUNPCKHDQ','mm','mm/m64','','Valid','Valid',0,'Unpack and interleave high-order\r\ndoublewords from mm and\r\nmm/m64 into mm.'),(1043,'66 0F 6A /r','PUNPCKHDQ','xmm1','xmm2/m128','','Valid','Valid',0,'Unpack and interleave high-order\r\ndoublewords from xmm1 and\r\nxmm2/m128 into xmm1.'),(1044,'66 0F 6D /r','PUNPCKHQDQ','xmm1','xmm2/m128','','Valid','Valid',0,'Unpack and interleave high-order\r\nquadwords from xmm1 and\r\nxmm2/m128 into xmm1.'),(1045,'0F 60 /r','PUNPCKLBW','mm','mm/m32','','Valid','Valid',0,'Interleave low-order bytes from\r\nmm and mm/m32 into mm.'),(1046,'66 0F 60 /r','PUNPCKLBW','xmm1','xmm2/m128','','Valid','Valid',0,'Interleave low-order bytes from\r\nxmm1 and xmm2/m128 into\r\nxmm1.'),(1047,'0F 61 /r','PUNPCKLWD','mm','mm/m32','','Valid','Valid',0,'Interleave low-order words from\r\nmm and mm/m32 into mm.'),(1048,'66 0F 61 /r','PUNPCKLWD','xmm1','xmm2/m128','','Valid','Valid',0,'Interleave low-order words from\r\nxmm1 and xmm2/m128 into\r\nxmm1.'),(1049,'0F 62 /r','PUNPCKLDQ','mm','mm/m32','','Valid','Valid',0,'Interleave low-order doublewords\r\nfrom mm and mm/m32 into mm.'),(1050,'66 0F 62 /r','PUNPCKLDQ','xmm1','xmm2/m128','','Valid','Valid',0,'Interleave low-order doublewords\r\nfrom xmm1 and xmm2/m128 into\r\nxmm1.'),(1051,'66 0F 6C /r','PUNPCKLQDQ','xmm1','xmm2/m128','','Valid','Valid',0,'Interleave low-order quadword\r\nfrom xmm1 and xmm2/m128 into\r\nxmm1 register.'),(1052,'FF /6','PUSH','r/m16','','','Valid','Valid',0,'Push r/m16.'),(1053,'FF /6','PUSH','r/m32','','','N.E.','Valid',0,'Push r/m32.'),(1054,'FF /6','PUSH','r/m64','','','Valid','N.E.',0,'Push r/m64. Default operand size 64-\r\nbits.'),(1055,'50+rw','PUSH','r16','','','Valid','Valid',0,'Push r16.'),(1056,'50+rd','PUSH','r16','','','Valid','Valid',0,'Push r16.'),(1057,'50+rd','PUSH','r32','','','N.E.','Valid',0,'Push r32.'),(1058,'50+rd','PUSH','r64','','','Valid','N.E.',0,'Push r64. Default operand size\r\n64-bits.'),(1059,'6A','PUSH','imm8','','','Valid','Valid',0,'Push sign-extended imm8. Stack\r\npointer is incremented by the size of\r\nstack pointer.'),(1060,'68','PUSH','imm16','','','Valid','Valid',0,'Push sign-extended imm16. Stack\r\npointer is incremented by the size of\r\nstack pointer.'),(1061,'68','PUSH','imm32','','','Valid','Valid',0,'Push sign-extended imm32. Stack\r\npointer is incremented by the size of\r\nstack pointer.'),(1062,'0E','PUSH','CS','','','Invalid','Valid',0,'Push CS.'),(1063,'16','PUSH','SS','','','Invalid','Valid',0,'Push SS.'),(1064,'1E','PUSH','DS','','','Invalid','Valid',0,'Push DS.'),(1065,'06','PUSH','ES','','','Invalid','Valid',0,'Push ES.'),(1066,'0F A0','PUSH','FS','','','Valid','Valid',0,'Push FS and decrement stack pointer\r\nby 16 bits.'),(1067,'0F A0','PUSH','FS','','','N.E.','Valid',0,'Push FS and decrement stack pointer\r\nby 32 bits.'),(1068,'0F A0','PUSH','FS','','','Valid','N.E.',0,'Push FS. Default operand size 64-bits.\r\n(66H override causes 16-bit\r\noperation).'),(1069,'0F A8c','PUSH','GS','','','Valid','Valid',0,'Push GS and decrement stack pointer\r\nby 16 bits.'),(1070,'0F A8','PUSH','GS','','','N.E.','Valid',0,'Push GS and decrement stack pointer\r\nby 32 bits.'),(1071,'0F A8','PUSH','GS','','','Valid','N.E.',0,'Push GS, default operand size 64-bits.\r\n(66H override causes 16-bit\r\noperation).'),(1072,'60','PUSHA','','','','Invalid','Valid',0,'Push AX, CX, DX, BX, original SP, BP, SI, and\r\nDI.'),(1073,'60','PUSHAD','','','','Invalid','Valid',0,'Push EAX, ECX, EDX, EBX, original ESP, EBP,\r\nESI, and EDI.'),(1074,'9C','PUSHF','','','','Valid','Valid',0,'Push lower 16 bits of EFLAGS.'),(1075,'9C','PUSHFD','','','','N.E.','Valid',0,'Push EFLAGS.'),(1076,'9C','PUSHFQ','','','','Valid','N.E.',0,'Push RFLAGS.'),(1077,'0F EF /r','PXOR','mm','mm/m64','','Valid','Valid',0,'Bitwise XOR of\r\nmm/m64 and mm.'),(1078,'66 0F EF /r','PXOR','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise XOR of\r\nxmm2/m128 and\r\nxmm1.'),(1079,'D0 /2','RCL','r/m8','1','','Valid','Valid',0,'Rotate 9 bits (CF, r/m8) left once.'),(1080,'REX + D0 /2','RCL','r/m8','1','','Valid','N.E.',0,'Rotate 9 bits (CF, r/m8) left once.'),(1081,'D2 /2','RCL','r/m8','CL','','Valid','Valid',0,'Rotate 9 bits (CF, r/m8) left CL times.'),(1082,'REX + D2 /2','RCL','r/m8','CL','','Valid','N.E.',0,'Rotate 9 bits (CF, r/m8) left CL times.'),(1083,'C0 /2 ib','RCL','r/m8','imm8','','Valid','Valid',0,'Rotate 9 bits (CF, r/m8) left imm8\r\ntimes.'),(1084,'REX + C0 /2 ib','RCL','r/m8','imm8','','Valid','N.E.',0,'Rotate 9 bits (CF, r/m8) left imm8\r\ntimes.'),(1085,'D1 /2','RCL','r/m16','1','','Valid','Valid',0,'Rotate 17 bits (CF, r/m16) left once.'),(1086,'D3 /2','RCL','r/m16','CL','','Valid','Valid',0,'Rotate 17 bits (CF, r/m16) left CL\r\ntimes.'),(1087,'C1 /2 ib','RCL','r/m16','imm8','','Valid','Valid',0,'Rotate 17 bits (CF, r/m16) left imm8\r\ntimes.'),(1088,'D1 /2','RCL','r/m32','1','','Valid','Valid',0,'Rotate 33 bits (CF, r/m32) left once.'),(1089,'REX.W + D1 /2','RCL','r/m64','1','','Valid','N.E.',0,'Rotate 65 bits (CF, r/m64) left once.\r\nUses a 6 bit count.'),(1090,'D3 /2','RCL','r/m32','CL','','Valid','Valid',0,'Rotate 33 bits (CF, r/m32) left CL\r\ntimes.'),(1091,'REX.W + D3 /2','RCL','r/m64','CL','','Valid','N.E.',0,'Rotate 65 bits (CF, r/m64) left CL\r\ntimes. Uses a 6 bit count.'),(1092,'C1 /2 ib','RCL','r/m32','imm8','','Valid','Valid',0,'Rotate 33 bits (CF, r/m32) left imm8\r\ntimes.'),(1093,'REX.W + C1 /2 ib','RCL','r/m64','imm8','','Valid','N.E.',0,'Rotate 65 bits (CF, r/m64) left imm8\r\ntimes. Uses a 6 bit count.'),(1094,'D0 /3','RCR','r/m8','1','','Valid','Valid',0,'Rotate 9 bits (CF, r/m8) right once.'),(1095,'REX + D0 /3','RCR','r/m8','1','','Valid','N.E.',0,'Rotate 9 bits (CF, r/m8) right once.'),(1096,'D2 /3','RCR','r/m8','CL','','Valid','Valid',0,'Rotate 9 bits (CF, r/m8) right CL\r\ntimes.'),(1097,'REX + D2 /3','RCR','r/m8','CL','','Valid','N.E.',0,'Rotate 9 bits (CF, r/m8) right CL\r\ntimes.'),(1098,'C0 /3 ib','RCR\r\n','r/m8','imm8','','Valid','Valid',0,'Rotate 9 bits (CF, r/m8) right imm8\r\ntimes.'),(1099,'REX + C0 /3 ib','RCR','r/m8','imm8','','Valid','N.E.',0,'Rotate 9 bits (CF, r/m8) right imm8\r\ntimes.'),(1100,'D1 /3','RCR','r/m16','1','','Valid','Valid',0,'Rotate 17 bits (CF, r/m16) right once.'),(1101,'D3 /3','RCR','r/m16','CL','','Valid','Valid',0,'Rotate 17 bits (CF, r/m16) right CL\r\ntimes.'),(1102,'C1 /3 ib','RCR','r/m16','imm8','','Valid','Valid',0,'Rotate 17 bits (CF, r/m16) right imm8\r\ntimes.'),(1103,'D1 /3','RCR','r/m32','1','','Valid','Valid',0,'Rotate 33 bits (CF, r/m32) right once.\r\nUses a 6 bit count.'),(1104,'REX.W + D1 /3','RCR','r/m64','1','','Valid','N.E.',0,'Rotate 65 bits (CF, r/m64) right once.\r\nUses a 6 bit count.'),(1105,'D3 /3','RCR','r/m32','CL','','Valid','Valid',0,'Rotate 33 bits (CF, r/m32) right CL\r\ntimes.'),(1106,'REX.W + D3 /3','RCR','r/m64','CL','','Valid','N.E.',0,'Rotate 65 bits (CF, r/m64) right CL\r\ntimes. Uses a 6 bit count.'),(1107,'C1 /3 ib','RCR','r/m32','imm8','','Valid','Valid',0,'Rotate 33 bits (CF, r/m32) right imm8\r\ntimes.'),(1108,'REX.W + C1 /3 ib','RCR','r/m64','imm8','','Valid','N.E.',0,'Rotate 65 bits (CF, r/m64) right imm8\r\ntimes. Uses a 6 bit count.'),(1109,'D0 /0','ROL','r/m8','1','','Valid','Valid',0,'Rotate 8 bits r/m8 left once.'),(1110,'REX + D0 /0','ROL','r/m8','1','','Valid','N.E.',0,'Rotate 8 bits r/m8 left once'),(1111,'D2 /0','ROL','r/m8','CL','','Valid','Valid',0,'Rotate 8 bits r/m8 left CL times.'),(1112,'REX + D2 /0','ROL','r/m8','CL','','Valid','N.E.',0,'Rotate 8 bits r/m8 left CL times.'),(1113,'C0 /0 ib','ROL','r/m8','imm8','','Valid','Valid',0,'Rotate 8 bits r/m8 left imm8 times.'),(1114,'REX + C0 /0 ib','ROL','r/m8','imm8','','Valid','N.E.',0,'Rotate 8 bits r/m8 left imm8 times.'),(1115,'D1 /0','ROL','r/m16','1','','Valid','Valid',0,'Rotate 16 bits r/m16 left once.'),(1116,'D3 /0','ROL','r/m16','CL','','Valid','Valid',0,'Rotate 16 bits r/m16 left CL times.'),(1117,'C1 /0 ib','ROL','r/m16','imm8','','Valid','Valid',0,'Rotate 16 bits r/m16 left imm8\r\ntimes.'),(1118,'D1 /0','ROL','r/m32','1','','Valid','Valid',0,'Rotate 32 bits r/m32 left once.'),(1119,'REX.W + D1 /0','ROL','r/m64','1','','Valid','N.E.',0,'Rotate 64 bits r/m64 left once. Uses\r\na 6 bit count.'),(1120,'D3 /0','ROL','r/m32','CL','','Valid','Valid',0,'Rotate 32 bits r/m32 left CL times.'),(1121,'REX.W + D3 /0','ROL','r/m64','CL','','Valid','N.E.',0,'Rotate 64 bits r/m64 left CL times.\r\nUses a 6 bit count.'),(1122,'C1 /0 ib','ROL','r/m32','imm8','','Valid','Valid',0,'Rotate 32 bits r/m32 left imm8\r\ntimes.'),(1123,'C1 /0 ib','ROL','r/m64','imm8','','Valid','N.E.',0,'Rotate 64 bits r/m64 left imm8\r\ntimes. Uses a 6 bit count.'),(1124,'D0 /1','ROR','r/m8','1','','Valid','Valid',0,'Rotate 8 bits r/m8 right once.'),(1125,'REX + D0 /1','ROR','r/m8','1','','Valid','N.E.',0,'Rotate 8 bits r/m8 right once.'),(1126,'D2 /1','ROR','r/m8','CL','','Valid','Valid',0,'Rotate 8 bits r/m8 right CL times.'),(1127,'REX + D2 /1','ROR','r/m8','CL','','Valid','N.E.',0,'Rotate 8 bits r/m8 right CL times.'),(1128,'C0 /1 ib','ROR','r/m8','imm8','','Valid','Valid',0,'Rotate 8 bits r/m16 right imm8\r\ntimes.'),(1129,'REX + C0 /1 ib','ROR','r/m8','imm8','','Valid','N.E.',0,'Rotate 8 bits r/m16 right imm8\r\ntimes.'),(1130,'D1 /1','ROR','r/m16','1','','Valid','Valid',0,'Rotate 16 bits r/m16 right once.'),(1131,'D3 /1','ROR','r/m16','CL','','Valid','Valid',0,'Rotate 16 bits r/m16 right CL times.'),(1132,'C1 /1 ib','ROR','r/m16','imm8','','Valid','Valid',0,'Rotate 16 bits r/m16 right imm8\r\ntimes.'),(1133,'D1 /1','ROR','r/m32','1','','Valid','Valid',0,'Rotate 32 bits r/m32 right once.'),(1134,'REX.W + D1 /1','ROR','r/m64','1','','Valid','N.E.',0,'Rotate 64 bits r/m64 right once. Uses\r\na 6 bit count.'),(1135,'D3 /1','ROR','r/m32','CL','','Valid','Valid',0,'Rotate 32 bits r/m32 right CL times.'),(1136,'REX.W + D3 /1','ROR','r/m64','CL','','Valid','N.E.',0,'Rotate 64 bits r/m64 right CL times.\r\nUses a 6 bit count.'),(1137,'C1 /1 ib','ROR','r/m32','imm8','','Valid','Valid',0,'Rotate 32 bits r/m32 right imm8\r\ntimes.'),(1138,'REX.W + C1 /1 ib','ROR','r/m64','imm8','','Valid','N.E.',0,'Rotate 64 bits r/m64 right imm8\r\ntimes. Uses a 6 bit count.'),(1139,'0F 53 /r','RCPPS','xmm1','xmm2/m128','','Valid','Valid',0,'Computes the approximate reciprocals\r\nof the packed single-precision floatingpoint\r\nvalues in xmm2/m128 and stores\r\nthe results in xmm1.'),(1140,'F3 0F 53 /r','RCPSS','xmm1','xmm2/m32','','Valid','Valid',0,'Computes the approximate reciprocal of\r\nthe scalar single-precision floating-point\r\nvalue in xmm2/m32 and stores the result\r\nin xmm1.'),(1141,'0F 32','RDMSR','','','','Valid','Valid',0,'Load MSR specified by ECX into\r\nEDX:EAX.'),(1142,'0F 33','RDPMC','','','','Valid','Valid',0,'Read performance-monitoring\r\ncounter specified by ECX into\r\nEDX:EAX.'),(1143,'0F 31','RDTSC','','','','Valid','Valid',0,'Read time-stamp counter into\r\nEDX:EAX.'),(1144,'F3 6C','REP INS','m8','DX','','Valid','Valid',0,'Input (E)CX bytes from port DX\r\ninto ES:[(E)DI].'),(1145,'F3 6C','REP INS','m8','DX','','Valid','N.E.',0,'Input RCX bytes from port DX\r\ninto [RDI].'),(1146,'F3 6D','REP INS','m16','DX','','Valid','Valid',0,'Input (E)CX words from port DX\r\ninto ES:[(E)DI.]'),(1147,'F3 6D','REP INS','m32','DX','','Valid','Valid',0,'Input (E)CX doublewords from\r\nport DX into ES:[(E)DI].'),(1148,'F3 6D','REP INS','r/m32','DX','','Valid','N.E.',0,'Input RCX default size from port\r\nDX into [RDI].'),(1149,'F3 A4','REP MOVS','m8','m8','','Valid','Valid',0,'Move (E)CX bytes from\r\nDS:[(E)SI] to ES:[(E)DI].'),(1150,'F3 REX.W A4','REP MOVS','m8','m8','','Valid','N.E.',0,'Move RCX bytes from [RSI] to\r\n[RDI].'),(1151,'F3 A5','REP MOVS','m16','m16','','Valid','Valid',0,'Move (E)CX words from\r\nDS:[(E)SI] to ES:[(E)DI].'),(1152,'F3 A5','REP MOVS','m32','m32','','Valid','Valid',0,'Move (E)CX doublewords from\r\nDS:[(E)SI] to ES:[(E)DI].'),(1153,'F3 REX.W A5','REP MOVS','m64','m64','','Valid','N.E.',0,'Move RCX quadwords from [RSI]\r\nto [RDI].'),(1154,'F3 6E','REP OUTS','DX','r/m8','','Valid','Valid',0,'Output (E)CX bytes from\r\nDS:[(E)SI] to port DX.'),(1155,'F3 REX.W 6E','REP OUTS','DX','r/m8','','Valid','N.E.',0,'Output RCX bytes from [RSI] to\r\nport DX.'),(1156,'F3 6F','REP OUTS','DX','r/m16','','Valid','Valid',0,'Output (E)CX words from\r\nDS:[(E)SI] to port DX.'),(1157,'F3 6F','REP OUTS','DX','r/m32','','Valid','Valid',0,'Output (E)CX doublewords from\r\nDS:[(E)SI] to port DX.'),(1158,'F3 REX.W 6F','REP OUTS','DX','r/m32','','Valid','N.E.',0,'Output RCX default size from\r\n[RSI] to port DX.'),(1159,'F3 AC','REP LODS','AL','','','Valid','Valid',0,'Load (E)CX bytes from DS:[(E)SI]\r\nto AL.'),(1160,'F3 REX.W AC','REP LODS','AL','','','Valid','N.E.',0,'Load RCX bytes from [RSI] to\r\nAL.'),(1161,'F3 AD','REP LODS','AX','','','Valid','Valid',0,'Load (E)CX words from DS:[(E)SI]\r\nto AX.'),(1162,'F3 AD','REP LODS','EAX','','','Valid','Valid',0,'Load (E)CX doublewords from\r\nDS:[(E)SI] to EAX.'),(1163,'F3 REX.W AD','REP LODS','RAX','','','Valid','N.E.',0,'Load RCX quadwords from [RSI]\r\nto RAX.'),(1164,'F3 AA','REP STOS','m8','','','Valid','Valid',0,'Fill (E)CX bytes at ES:[(E)DI] with\r\nAL.'),(1165,'F3 REX.W AA','REP STOS','m8','','','Valid','N.E.',0,'Fill RCX bytes at [RDI] with AL.'),(1166,'F3 AB','REP STOS','m16','','','Valid','Valid',0,'Fill (E)CX words at ES:[(E)DI]\r\nwith AX.'),(1167,'F3 AB','REP STOS','m32','','','Valid','Valid',0,'Fill (E)CX doublewords at\r\nES:[(E)DI] with EAX.'),(1168,'F3 REX.W AB','REP STOS','m64','','','Valid','N.E.',0,'Fill RCX quadwords at [RDI] with\r\nRAX.'),(1169,'F3 A6','REPE CMPS','m8','m8','','Valid','Valid',0,'Find nonmatching bytes in\r\nES:[(E)DI] and DS:[(E)SI].'),(1170,'F3 REX.W A6','REPE CMPS','m8','m8','','Valid','N.E.',0,'Find non-matching bytes in\r\n[RDI] and [RSI].'),(1171,'F3 A7','REPE CMPS','m16','m16','','Valid','Valid',0,'Find nonmatching words in\r\nES:[(E)DI] and DS:[(E)SI].'),(1172,'F3 A7','REPE CMPS','m32','m32','','Valid','Valid',0,'Find nonmatching doublewords\r\nin ES:[(E)DI] and DS:[(E)SI].'),(1173,'F3 REX.W A7','REPE CMPS','m64','m64','','Valid','N.E.',0,'Find non-matching quadwords\r\nin [RDI] and [RSI].'),(1174,'F3 AE','REPE SCAS','m8','','','Valid','Valid',0,'Find non-AL byte starting at\r\nES:[(E)DI].'),(1175,'F3 REX.W AE','REPE SCAS','m8','','','Valid','N.E.',0,'Find non-AL byte starting at\r\n[RDI].'),(1176,'F3 AF','REPE SCAS','m16','','','Valid','Valid',0,'Find non-AX word starting at\r\nES:[(E)DI].'),(1177,'F3 AF','REPE SCAS','m32','','','Valid','Valid',0,'Find non-EAX doubleword\r\nstarting at ES:[(E)DI].'),(1178,'F3 REX.W AF','REPE SCAS','m64','','','Valid','N.E.',0,'Find non-RAX quadword\r\nstarting at [RDI].'),(1179,'F2 A6','REPNE CMPS','m8','m8','','Valid','Valid',0,'Find matching bytes in ES:[(E)DI]\r\nand DS:[(E)SI].'),(1180,'F2 REX.W A6','REPNE CMPS','m8','m8','','Valid','N.E.',0,'Find matching bytes in [RDI] and\r\n[RSI].'),(1181,'F2 A7','REPNE CMPS','m16','m16','','Valid','Valid',0,'Find matching words in\r\nES:[(E)DI] and DS:[(E)SI].'),(1182,'F2 A7','REPNE CMPS','m32','m32','','Valid','Valid',0,'Find matching doublewords in\r\nES:[(E)DI] and DS:[(E)SI].'),(1183,'F2 REX.W A7','REPNE CMPS','m64','m64','','Valid','N.E.',0,'Find matching doublewords in\r\n[RDI] and [RSI].'),(1184,'F2 AE','REPNE SCAS','m8','','','Valid','Valid',0,'Find AL, starting at ES:[(E)DI].'),(1185,'F2 REX.W AE','REPNE SCAS','m8','','','Valid','N.E.',0,'Find AL, starting at [RDI].'),(1186,'F2 AF','REPNE SCAS','m16','','','Valid','Valid',0,'Find AX, starting at ES:[(E)DI].'),(1187,'F2 AF','REPNE SCAS','m32','','','Valid','Valid',0,'Find EAX, starting at ES:[(E)DI].'),(1188,'F2 REX.W AF','REPNE SCAS','m64','','','Valid','N.E.',0,'Find RAX, starting at [RDI].'),(1189,'C3','RET','','','','Valid','Valid',0,'Near return to calling procedure.'),(1190,'CB','RET','','','','Valid','Valid',0,'Far return to calling procedure.'),(1191,'C2 iw','RET','imm16','','','Valid','Valid',0,'Near return to calling procedure and pop\r\nimm16 bytes from stack.'),(1192,'CA iw','RET','imm16','','','Valid','Valid',0,'Far return to calling procedure and pop\r\nimm16 bytes from stack.'),(1193,'0F AA','RSM','','','','Invalid','Valid',0,'Resume operation of interrupted\r\nprogram.'),(1194,'0F 52 /r','RSQRTPS','xmm1','xmm2/m128','','Valid','Valid',0,'Computes the approximate reciprocals\r\nof the square roots of the packed\r\nsingle-precision floating-point values\r\nin xmm2/m128 and stores the results\r\nin xmm1.'),(1195,'F3 0F 52 /r','RSQRTSS','xmm1','xmm2/m32','','Valid','Valid',0,'Computes the approximate reciprocal of\r\nthe square root of the low singleprecision\r\nfloating-point value in\r\nxmm2/m32 and stores the results in\r\nxmm1.'),(1196,'9E','SAHF','','','','Invalid','Valid',0,'Loads SF, ZF, AF, PF, and CF from AH\r\ninto EFLAGS register.'),(1197,'D0 /4','SAL','r/m8','1','','Valid','Valid',0,'Multiply r/m8 by 2, once.'),(1198,'REX + D0 /4','SAL','r/m8','1','','Valid','N.E.',0,'Multiply r/m8 by 2, once.'),(1199,'D2 /4','SAL','r/m8','CL','','Valid','Valid',0,'Multiply r/m8 by 2, CL times.'),(1200,'REX + D2 /4','SAL','r/m8','CL','','Valid','N.E.',0,'Multiply r/m8 by 2, CL times.'),(1201,'C0 /4 ib','SAL','r/m8','imm8','','Valid','Valid',0,'Multiply r/m8 by 2, imm8\r\ntimes.'),(1202,'REX + C0 /4 ib','SAL','r/m8','imm8','','Valid','N.E.',0,'Multiply r/m8 by 2, imm8 times.'),(1203,'D1 /4','SAL','r/m16','1','','Valid','Valid',0,'Multiply r/m16 by 2, once.'),(1204,'D3 /4','SAL','r/m16','CL','','Valid','Valid',0,'Multiply r/m16 by 2, CL times.'),(1205,'C1 /4 ib','SAL','r/m16','r/m16','','Valid','Valid',0,'Multiply r/m16 by 2, imm8\r\ntimes.'),(1206,'D1 /4','SAL','r/m32','1','','Valid','Valid',0,'Multiply r/m32 by 2, once.'),(1207,'REX.W + D1 /4','SAL','r/m64','1','','Valid','N.E.',0,'Multiply r/m64 by 2, once.'),(1208,'D3 /4','SAL','r/m32','CL','','Valid','Valid',0,'Multiply r/m32 by 2, CL times.'),(1209,'REX.W + D3 /4','SAL','r/m64','CL','','Valid','N.E.',0,'Multiply r/m64 by 2, CL times.'),(1210,'C1 /4 ib','SAL','r/m32','imm8','','Valid','Valid',0,'Multiply r/m32 by 2, imm8\r\ntimes.'),(1211,'REX.W + C1 /4 ib','SAL','r/m64','imm8','','Valid','N.E.',0,'Multiply r/m64 by 2, imm8\r\ntimes'),(1212,'D0 /7','SAR','r/m8','1','','Valid','Valid',0,'Signed divide* r/m8 by 2,\r\nonce.'),(1213,'REX + D0 /7','SAR','r/m8','1','','Valid','N.E.',0,'Signed divide* r/m8 by 2,\r\nonce.'),(1214,'D2 /7','SAR','r/m8','CL','','Valid','Valid',0,'Signed divide* r/m8 by 2, CL\r\ntimes.'),(1215,'REX + D2 /7','SAR','r/m8','CL','','Valid','N.E.',0,'Signed divide* r/m8 by 2, CL\r\ntimes.'),(1216,'C0 /7 ib','SAR','r/m8','imm8','','Valid','Valid',0,'Signed divide* r/m8 by 2,'),(1217,'REX + C0 /7 ib','SAR','r/m8','imm8','','Valid','N.E.',0,'Signed divide* r/m8 by 2,\r\nimm8 times.'),(1218,'D1 /7','SAR','r/m16','1','','Valid','Valid',0,'Signed divide* r/m16 by 2,\r\nonce.'),(1219,'D3 /7','SAR','r/m16','CL','','Valid','Valid',0,'Signed divide* r/m16 by 2, CL\r\ntimes.'),(1220,'C1 /7 ib','SAR','r/m16','imm8','','Valid','Valid',0,'Signed divide* r/m16 by 2,\r\nimm8 times.'),(1221,'D1 /7','SAR','r/m32','1','','Valid','Valid',0,'Signed divide* r/m32 by 2,\r\nonce.'),(1222,'REX.W + D1 /7','SAR','r/m64','1','','Valid','N.E.',0,'Signed divide* r/m64 by 2,\r\nonce.'),(1223,'D3 /7','SAR','r/m32','CL','','Valid','Valid',0,'Signed divide* r/m32 by 2, CL\r\ntimes.'),(1224,'REX.W + D3 /7','SAR','r/m64','CL','','Valid','N.E.',0,'Signed divide* r/m64 by 2, CL\r\ntimes.'),(1225,'C1 /7 ib','SAR','r/m32','imm8','','Valid','Valid',0,'Signed divide* r/m32 by 2,\r\nimm8 times.'),(1226,'REX.W + C1 /7 ib','SAR','r/m64','imm8','','Valid','N.E.',0,'Signed divide* r/m64 by 2,\r\nimm8 times'),(1227,'D0 /4','SHL','r/m8','1','','Valid','Valid',0,'Multiply r/m8 by 2, once.'),(1228,'REX + D0 /4','SHL','r/m8','1','','Valid','Valid',0,'Multiply r/m8 by 2, once.'),(1229,'REX + D0 /4','SHL','r/m8','1','','Valid','N.E.',0,'Multiply r/m8 by 2, once.'),(1230,'D2 /4','SHL','r/m8','CL','','Valid','Valid',0,'Multiply r/m8 by 2, CL times.'),(1231,'REX + D2 /4','SHL','r/m8','CL','','Valid','N.E.',0,'Multiply r/m8 by 2, CL times.'),(1232,'C0 /4 ib','SHL','r/m8','imm8','','Valid','Valid',0,'Multiply r/m8 by 2, imm8\r\ntimes.'),(1233,'REX + C0 /4 ib','SHL','r/m8','imm8','','Valid','N.E.',0,'Multiply r/m8 by 2, imm8\r\ntimes.'),(1234,'D1 /4','SHL','r/m16','1','','Valid','Valid',0,'Multiply r/m16 by 2, once.'),(1235,'D3 /4','SHL','r/m16','CL','','Valid','Valid',0,'Multiply r/m16 by 2, CL times.'),(1236,'C1 /4 ib','SHL','r/m16','imm8','','Valid','Valid',0,'Multiply r/m16 by 2, imm8\r\ntimes.'),(1237,'D1 /4','SHL','r/m32','1','','Valid','Valid',0,'Multiply r/m32 by 2, once.'),(1238,'REX.W + D1 /4','SHL','r/m64','1','','Valid','N.E.',0,'Multiply r/m64 by 2, once.'),(1239,'D3 /4','SHL','r/m32','CL','','Valid','Valid',0,'Multiply r/m32 by 2, CL times.'),(1240,'REX.W + D3 /4','SHL','r/m64','CL','','Valid','N.E',0,'Multiply r/m64 by 2, CL times.'),(1241,'C1 /4 ib','SHL','r/m32','imm8','','Valid','Valid',0,'Multiply r/m32 by 2, imm8\r\ntimes.'),(1242,'REX.W + C1 /4 ib','SHL','r/m64','imm8','','Valid','N.E.',0,'Multiply r/m64 by 2, imm8\r\ntimes.'),(1243,'D0 /5','SHR','r/m8','1','','Valid','Valid',0,'Unsigned divide r/m8 by 2,\r\nonce.'),(1244,'REX + D0 /5','SHR','r/m8','1','','Valid','N.E.',0,'Unsigned divide r/m8 by 2,\r\nonce.'),(1245,'D2 /5','SHR','r/m8','CL','','Valid','Valid',0,'Unsigned divide r/m8 by 2, CL\r\ntimes.'),(1246,'REX + D2 /5','SHR','r/m8','CL','','Valid','N.E.',0,'Unsigned divide r/m8 by 2, CL\r\ntimes.'),(1247,'C0 /5 ib','SHR','r/m8','imm8','','Valid','Valid',0,'Unsigned divide r/m8 by 2,\r\nimm8 times.'),(1248,'REX + C0 /5 ib','SHR','r/m8','imm8','','Valid','N.E.',0,'Unsigned divide r/m8 by 2,\r\nimm8 times.'),(1249,'D1 /5','SHR','r/m16','1','','Valid','Valid',0,'Unsigned divide r/m16 by 2,\r\nonce.'),(1250,'D3 /5','SHR','r/m16','CL','','Valid','Valid',0,'Unsigned divide r/m16 by 2,\r\nCL times'),(1251,'C1 /5 ib','SHR','r/m16','imm8','','Valid','Valid',0,'Unsigned divide r/m16 by 2,\r\nimm8 times.'),(1252,'D1 /5','SHR','r/m32','1','','Valid','Valid',0,'Unsigned divide r/m32 by 2,\r\nonce.'),(1253,'REX.W + D1 /5','SHR','r/m64','1','','Valid','N.E.',0,'Unsigned divide r/m64 by 2,\r\nonce.'),(1254,'D3 /5','SHR','r/m32','CL','','Valid','Valid',0,'Unsigned divide r/m32 by 2,\r\nCL times.'),(1255,'REX.W + D3 /5','SHR','r/m64','CL','','Valid','N.E.',0,'Unsigned divide r/m64 by 2,\r\nCL times.'),(1256,'C1 /5 ib','SHR','r/m32','imm8','','Valid','Valid',0,'Unsigned divide r/m32 by 2,\r\nimm8 times.'),(1257,'REX.W + C1 /5 ib','SHR','r/m64','imm8','','Valid','N.E.',0,'Unsigned divide r/m64 by 2,\r\nimm8 times.'),(1258,'1C ib','SBB','AL','imm8','','Valid','Valid',0,'Subtract with borrow imm8'),(1259,'1D iw','SBB','AX','imm16','','Valid','Valid',0,'Subtract with borrow imm16\r\nfrom AX.'),(1260,'1D id','SBB','EAX','imm32','','Valid','Valid',0,'Subtract with borrow imm32\r\nfrom EAX.'),(1261,'REX.W + 1D id','SBB','RAX','imm32','','Valid','N.E.',0,'Subtract with borrow signextended\r\nimm.32 to 64-bits\r\nfrom RAX.'),(1262,'80 /3 ib','SBB','r/m8','imm8','','Valid','Valid',0,'Subtract with borrow imm8\r\nfrom r/m8.'),(1263,'REX + 80 /3 ib','SBB','r/m8','imm8','','Valid','N.E.',0,'Subtract with borrow imm8\r\nfrom r/m8.'),(1264,'81 /3 iw','SBB','r/m16','imm16','','Valid','Valid',0,'Subtract with borrow imm16\r\nfrom r/m16.'),(1265,'81 /3 id','SBB','r/m32','imm32','','Valid','Valid',0,'Subtract with borrow imm32\r\nfrom r/m32.'),(1266,'REX.W + 81 /3 id','SBB','r/m64','imm32','','Valid','N.E.',0,'Subtract with borrow signextended\r\nimm32 to 64-bits\r\nfrom r/m64.'),(1267,'83 /3 ib','SBB','r/m16','imm8','','Valid','Valid',0,'Subtract with borrow signextended\r\nimm8 from r/m16.'),(1268,'83 /3 ib','SBB','r/m32','imm8','','Valid','Valid',0,'Subtract with borrow signextended\r\nimm8 from r/m32.'),(1269,'REX.W + 83 /3 ib','SBB','r/m64','imm8','','Valid','N.E.',0,'Subtract with borrow signextended\r\nimm8 from r/m64.'),(1270,'18 /r','SBB','r/m8','r8','','Valid','Valid',0,'Subtract with borrow r8\r\nfrom r/m8.'),(1271,'REX + 18 /r','SBB','r/m8','r8','','Valid','N.E.',0,'Subtract with borrow r8\r\nfrom r/m8.'),(1272,'19 /r','SBB','r/m16','r16','','Valid','Valid',0,'Subtract with borrow r16\r\nfrom r/m16.'),(1273,'19 /r','SBB','r/m32','r32','','Valid','Valid',0,'Subtract with borrow r32\r\nfrom r/m32.'),(1274,'REX.W + 19 /r','SBB','r/m64','r64','','Valid','N.E.',0,'Subtract with borrow r64\r\nfrom r/m64.'),(1275,'1A /r','SBB','r8','r/m8','','Valid','Valid',0,'Subtract with borrow r/m8\r\nfrom r8.'),(1276,'REX + 1A /r','SBB','r8','r/m8','','Valid','N.E.',0,'Subtract with borrow r/m8\r\nfrom r8.'),(1277,'1B /r','SBB','r16','r/m16','','Valid','Valid',0,'Subtract with borrow r/m16\r\nfrom r16.'),(1278,'1B /r','SBB','r32','r/m32','','Valid','Valid',0,'Subtract with borrow r/m32\r\nfrom r32.'),(1279,'REX.W + 1B /r','SBB','r64','r/m64','','Valid','N.E.',0,'Subtract with borrow r/m64\r\nfrom r64.'),(1280,'AE','SCAS','m8','','','Valid','Valid',0,'Compare AL with byte at ES:(E)DI or RDI,\r\nthen set status flags.'),(1281,'AF','SCAS','m16','','','Valid','Valid',0,'Compare AX with word at ES:(E)DI or\r\nRDI, then set status flags.'),(1282,'AF','SCAS','m32','','','Valid','Valid',0,'Compare EAX with doubleword at\r\nES(E)DI or RDI then set status flags.'),(1283,'REX.W + AF','SCAS','m64','','','Valid','N.E.',0,'Compare RAX with quadword at RDI or\r\nEDI then set status flags.'),(1284,'AE','SCASB','','','','Valid','Valid',0,'Compare AL with byte at ES:(E)DI or RDI\r\nthen set status flags.'),(1285,'AF','SCASW','','','','Valid','Valid',0,'Compare AX with word at ES:(E)DI or RDI\r\nthen set status flags.'),(1286,'AF','SCASD','','','','Valid','Valid',0,'Compare EAX with doubleword at\r\nES:(E)DI or RDI then set status flags.'),(1287,'REX.W + AF','SCASQ','','','','Valid','N.E.',0,'Compare RAX with quadword at RDI or\r\nEDI then set status flags.'),(1288,'0F 97','SETA','r/m8','','','Valid','Valid',0,'Set byte if above (CF=0 and\r\nZF=0).'),(1289,'REX + 0F 97','SETA','r/m8','','','Valid','N.E.',0,'Set byte if above (CF=0 and\r\nZF=0).'),(1290,'0F 93','SETAE','r/m8','','','Valid','Valid',0,'Set byte if above or equal (CF=0).'),(1291,'REX + 0F 93','SETAE','r/m8','','','Valid','N.E.',0,'Set byte if above or equal (CF=0).'),(1292,'0F 92','SETB','r/m8','','','Valid','Valid',0,'Set byte if below (CF=1).'),(1293,'REX + 0F 92','SETB','r/m8','','','Valid','N.E.',0,'Set byte if below (CF=1).'),(1294,'0F 96','SETBE','r/m8','','','Valid','Valid',0,'Set byte if below or equal (CF=1\r\nor ZF=1).'),(1295,'REX + 0F 96','SETBE','r/m8','','','Valid','N.E.',0,'Set byte if below or equal (CF=1\r\nor ZF=1).'),(1296,'0F 92','SETC','r/m8','','','Valid','Valid',0,'Set byte if carry (CF=1).'),(1297,'REX + 0F 92','SETC','r/m8','','','Valid','N.E.',0,'Set byte if carry (CF=1).'),(1298,'0F 94','SETE','r/m8','','','Valid','Valid',0,'Set byte if equal (ZF=1).'),(1299,'REX + 0F 94','SETE','r/m8','','','Valid','N.E.',0,'Set byte if equal (ZF=1).'),(1300,'0F 9F','SETG','r/m8','','','Valid','Valid',0,'Set byte if greater (ZF=0 and\r\nSF=OF).'),(1301,'REX + 0F 9F','SETG','r/m8','','','Valid','N.E.',0,'Set byte if greater (ZF=0 and\r\nSF=OF).'),(1302,'0F 9D','SETGE','r/m8','','','Valid','Valid',0,'Set byte if greater or equal\r\n(SF=OF).'),(1303,'REX + 0F 9D','SETGE','r/m8','','','Valid','N.E.',0,'Set byte if greater or equal\r\n(SF=OF).'),(1304,'0F 9C','SETL','r/m8','','','Valid','Valid',0,'Set byte if less (SF≠ OF).'),(1305,'REX + 0F 9C','SETL','r/m8','','','Valid','N.E.',0,'Set byte if less (SF≠ OF).'),(1306,'0F 9E','SETLE','r/m8','','','Valid','Valid',0,'Set byte if less or equal (ZF=1 or\r\nSF≠ OF).'),(1307,'REX + 0F 9E','SETLE','r/m8','','','Valid','N.E.',0,'Set byte if less or equal (ZF=1 or\r\nSF≠ OF).'),(1308,'0F 96','SETNA','r/m8','','','Valid','Valid',0,'Set byte if not above (CF=1 or\r\nZF=1).'),(1309,'REX + 0F 96','SETNA','r/m8','','','Valid','N.E.',0,'Set byte if not above (CF=1 or\r\nZF=1).'),(1310,'0F 92','SETNAE','r/m8','','','Valid','Valid',0,'Set byte if not above or equal\r\n(CF=1).'),(1311,'REX + 0F 92','SETNAE','r/m8','','','Valid','N.E.',0,'Set byte if not above or equal\r\n(CF=1).'),(1312,'0F 93','SETNB','r/m8','','','Valid','Valid',0,'Set byte if not below (CF=0).'),(1313,'REX + 0F 93','SETNB','r/m8','','','Valid','N.E.',0,'Set byte if not below (CF=0).'),(1314,'0F 97','SETNBE','r/m8','','','Valid','Valid',0,'Set byte if not below or equal\r\n(CF=0 and ZF=0).'),(1315,'REX + 0F 97','SETNBE','r/m8','','','Valid','N.E.',0,'Set byte if not below or equal\r\n(CF=0 and ZF=0).'),(1316,'0F 93','SETNC','r/m8','','','Valid','Valid',0,'Set byte if not carry (CF=0).'),(1317,'REX + 0F 93','SETNC','r/m8','','','Valid','N.E.',0,'Set byte if not carry (CF=0).'),(1318,'0F 95','SETNE','r/m8','','','Valid','Valid',0,'Set byte if not equal (ZF=0).'),(1319,'REX + 0F 95','SETNE','r/m8','','','Valid','N.E.',0,'Set byte if not equal (ZF=0).'),(1320,'0F 9E','SETNG','r/m8','','','Valid','Valid',0,'Set byte if not greater (ZF=1 or\r\nSF≠ OF)'),(1321,'REX + 0F 9E','SETNG','r/m8','','','Valid','N.E.',0,'Set byte if not greater (ZF=1 or\r\nSF≠ OF).'),(1322,'0F 9C','SETNGE','r/m8','','','Valid','Valid',0,'Set byte if not greater or equal\r\n(SF≠ OF).'),(1323,'REX + 0F 9C','SETNGE','r/m8','','','Valid','N.E.',0,'Set byte if not greater or equal\r\n(SF≠ OF).'),(1324,'0F 9D','SETNL','r/m8','','','Valid','Valid',0,'Set byte if not less (SF=OF).'),(1325,'REX + 0F 9D','SETNL','r/m8','','','Valid','N.E.',0,'Set byte if not less (SF=OF).'),(1326,'0F 9F','SETNLE','r/m8','','','Valid','Valid',0,'Set byte if not less or equal (ZF=0\r\nand SF=OF).'),(1327,'REX + 0F 9F','SETNLE','r/m8','','','Valid','N.E.',0,'Set byte if not less or equal (ZF=0\r\nand SF=OF).'),(1328,'0F 91','SETNO','r/m8','','','Valid','Valid',0,'Set byte if not overflow (OF=0).'),(1329,'REX + 0F 91','SETNO','r/m8','','','Valid','N.E.',0,'Set byte if not overflow (OF=0).'),(1330,'0F 9B','SETNP','r/m8','','','Valid','Valid',0,'Set byte if not parity (PF=0).'),(1331,'REX + 0F 9B','SETNP','r/m8','','','Valid','N.E.',0,'Set byte if not parity (PF=0).'),(1332,'0F 99','SETNS','r/m8','','','Valid','Valid',0,'Set byte if not sign (SF=0).'),(1333,'REX + 0F 99','SETNS','r/m8','','','Valid','N.E.',0,'Set byte if not sign (SF=0).'),(1334,'0F 95','SETNZ','r/m8','','','Valid','Valid',0,'Set byte if not zero (ZF=0).'),(1335,'REX + 0F 95','SETNZ','r/m8','','','Valid','N.E.',0,'Set byte if not zero (ZF=0).'),(1336,'0F 90','SETO','r/m8','','','Valid','Valid',0,'Set byte if overflow (OF=1)'),(1337,'REX + 0F 90','SETO','r/m8','','','Valid','N.E.',0,'Set byte if overflow (OF=1).'),(1338,'0F 9A','SETP','r/m8','','','Valid','Valid',0,'Set byte if parity (PF=1).'),(1339,'REX + 0F 9A','SETP','r/m8','','','Valid','N.E.',0,'Set byte if parity (PF=1).'),(1340,'0F 9A','SETPE','r/m8','','','Valid','Valid',0,'Set byte if parity even (PF=1).'),(1341,'REX + 0F 9A','SETPE','r/m8','','','Valid','N.E.',0,'Set byte if parity even (PF=1).'),(1342,'0F 9B','SETPO','r/m8','','','Valid','Valid',0,'Set byte if parity odd (PF=0).'),(1343,'REX + 0F 9B','SETPO','r/m8','','','Valid','N.E.',0,'Set byte if parity odd (PF=0).'),(1344,'0F 98','SETS','r/m8','','','Valid','Valid',0,'Set byte if sign (SF=1).'),(1345,'REX + 0F 98','SETS','r/m8','','','Valid','N.E.',0,'Set byte if sign (SF=1).'),(1346,'0F 94','SETZ','r/m8','','','Valid','Valid',0,'Set byte if zero (ZF=1).'),(1347,'REX + 0F 94','SETZ','r/m8','','','Valid','N.E.',0,'Set byte if zero (ZF=1).'),(1348,'0F AE /7','SFENCE','','','','Valid','Valid',0,'Serializes store operations.'),(1349,'0F 01 /0','SGDT','m','','','Valid','Valid',0,'Store GDTR to m.'),(1350,'0F A4','SHLD','r/m16','r16','imm8','Valid','Valid',0,'Shift r/m16 to left imm8\r\nplaces while shifting bits\r\nfrom r16 in from the right.'),(1351,'0F A5','SHLD','r/m16','r16','CL','Valid','Valid',0,'Shift r/m16 to left CL places\r\nwhile shifting bits from r16\r\nin from the right.'),(1352,'0F A4','SHLD','r/m32','r32','imm8','Valid','Valid',0,'Shift r/m32 to left imm8\r\nplaces while shifting bits\r\nfrom r32 in from the right.'),(1353,'REX.W + 0F A4','SHLD','r/m64','r64','imm8','Valid','N.E.',0,'Shift r/m64 to left imm8\r\nplaces while shifting bits\r\nfrom r64 in from the right.'),(1354,'0F A5','SHLD','r/m32','r32','CL','Valid','Valid',0,'Shift r/m32 to left CL places\r\nwhile shifting bits from r32\r\nin from the right.'),(1355,'REX.W + 0F A5','SHLD','r/m64','r64','CL','Valid','N.E.',0,'Shift r/m64 to left CL places\r\nwhile shifting bits from r64\r\nin from the right.'),(1356,'0F AC','SHRD','r/m16','r16','imm8','Valid','Valid',0,'Shift r/m16 to right imm8 places\r\nwhile shifting bits from r16 in\r\nfrom the left.'),(1357,'0F AD','SHRD','r/m16','r16','CL','Valid','Valid',0,'Shift r/m16 to right CL places\r\nwhile shifting bits from r16 in\r\nfrom the left.'),(1358,'0F AC','SHRD','r/m32','r32','imm8','Valid','Valid',0,'Shift r/m32 to right imm8 places\r\nwhile shifting bits from r32 in\r\nfrom the left.'),(1359,'REX.W + 0F AC','SHRD','r/m64','r64','imm8','Valid','N.E.',0,'Shift r/m64 to right imm8 places\r\nwhile shifting bits from r64 in\r\nfrom the left.'),(1360,'0F AD','SHRD','r/m32','r32','CL','Valid','Valid',0,'Shift r/m32 to right CL places\r\nwhile shifting bits from r32 in\r\nfrom the left.'),(1361,'REX.W + 0F AD','SHRD','r/m64','r64','CL','Valid','N.E.',0,'Shift r/m64 to right CL places\r\nwhile shifting bits from r64 in\r\nfrom the left.'),(1362,'66 0F C6 /r ib','SHUFPD','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Shuffle packed double-precision\r\nfloating-point values selected by\r\nimm8 from xmm1 and\r\nxmm2/m128 to xmm1.'),(1363,'0F C6 /r ib','SHUFPS','xmm1','xmm2/m128','imm8','Valid','Valid',0,'Shuffle packed single-precision\r\nfloating-point values selected by\r\nimm8 from xmm1 and\r\nxmm1/m128 to xmm1.'),(1364,'0F 01 /1','SIDT','m','','','Valid','Valid',0,'Store IDTR to m.'),(1365,'0F 00 /0','SLDT','r/m16','','','Valid','Valid',0,'Stores segment selector from LDTR\r\nin r/m16.'),(1366,'REX.W + 0F 00 /0','SLDT','r64/m16','','','Valid','Valid',0,'Stores segment selector from LDTR\r\nin r64/m16.'),(1367,'0F 01 /4','SMSW','r/m16','','','Valid','Valid',0,'Store machine status word to r/m16.'),(1368,'0F 01 /4','SMSW','r32/m16','','','Valid','Valid',0,'Store machine status word in low-order\r\n16 bits of r32/m16; high-order 16 bits\r\nof r32 are undefined.'),(1369,'REX.W + 0F 01 /4','SMSW','r64/m16','','','Valid','Valid',0,'Store machine status word in low-order\r\n16 bits of r64/m16; high-order 16 bits\r\nof r32 are undefined.'),(1370,'66 0F 51 /r','SQRTPD','xmm1','xmm2/m128','','Valid','Valid',0,'Computes square roots of the\r\npacked double-precision floatingpoint\r\nvalues in xmm2/m128 and\r\nstores the results in xmm1.'),(1371,'0F 51 /r','SQRTPS','xmm1','xmm2/m128','','Valid','Valid',0,'Computes square roots of the packed\r\nsingle-precision floating-point values in\r\nxmm2/m128 and stores the results in\r\nxmm1.'),(1372,'F2 0F 51 /r','SQRTSD','xmm1','xmm2/m64','','Valid','Valid',0,'Computes square root of the\r\nlow double-precision floatingpoint\r\nvalue in xmm2/m64 and\r\nstores the results in xmm1.'),(1373,'F3 0F 51 /r','SQRTSS','xmm1','xmm2/m3','','Valid','Valid',0,'Computes square root of the low\r\nsingle-precision floating-point value\r\nin xmm2/m32 and stores the\r\nresults in xmm1.'),(1374,'F9','STC','','','','Valid','Valid',0,'Set CF flag.'),(1375,'FD','STD','','','','Valid','Valid',0,'Set DF flag.'),(1376,'FB','STI','','','','Valid','Valid',0,'Set interrupt flag; external, maskable\r\ninterrupts enabled at the end of the\r\nnext instruction.'),(1377,'0F AE /3','STMXCSR','m32','','','Valid','Valid',0,'Store contents of MXCSR register to\r\nm32.'),(1378,'AA','STOS','m8','','','Valid','Valid',0,'For legacy mode, store AL at address\r\nES:(E)DI; For 64-bit mode store AL at\r\naddress RDI or EDI.'),(1379,'AB','STOS','m16','','','Valid','Valid',0,'For legacy mode, store AX at address\r\nES:(E)DI; For 64-bit mode store AX at\r\naddress RDI or EDI.'),(1380,'AB','STOS','m32','','','Valid','Valid',0,'For legacy mode, store EAX at address\r\nES:(E)DI; For 64-bit mode store EAX at\r\naddress RDI or EDI.'),(1381,'REX.W + AB','STOS','m64','','','Valid','N.E.',0,'Store RAX at address RDI or EDI.'),(1382,'AA','STOSB','','','','Valid','Valid',0,'For legacy mode, store AL at address\r\nES:(E)DI; For 64-bit mode store AL at\r\naddress RDI or EDI.'),(1383,'AB','STOSW','','','','Valid','Valid',0,'For legacy mode, store AX at address\r\nES:(E)DI; For 64-bit mode store AX at\r\naddress RDI or EDI.'),(1384,'AB','STOSDc','','\r\n','','Valid','Valid',0,'For legacy mode, store EAX at address\r\nES:(E)DI; For 64-bit mode store EAX at\r\naddress RDI or EDI.'),(1385,'REX.W + AB','STOSQ','','','','Valid','N.E.',0,'Store RAX at address RDI or EDI.'),(1386,'0F 00 /1','STR','r/m16','','','Valid','Valid',0,'Stores segment selector from TR in\r\nr/m16.'),(1387,'2C ib','SUB','AL','imm8','','Valid','Valid',0,'Subtract imm8 from AL.'),(1388,'2D iw','SUB','AX','imm16','','Valid','Valid',0,'Subtract imm16 from AX.'),(1389,'2D id','SUB','EAX','imm32','','Valid','Valid',0,'Subtract imm32 from EAX.'),(1390,'REX.W + 2D id','SUB','RAX','imm32','','Valid','N.E.',0,'Subtract imm32 signextended\r\nto 64-bits from\r\nRAX.'),(1391,'80 /5 ib','SUB','r/m8','imm8','','Valid','Valid',0,'Subtract imm8 from r/m8.'),(1392,'REX + 80 /5 ib','SUB','r/m8','imm8','','Valid','N.E.',0,'Subtract imm8 from r/m8.'),(1393,'81 /5 iw','SUB','r/m16','imm16','','Valid','Valid',0,'Subtract imm16 from r/m16.'),(1394,'81 /5 id','SUB','r/m32','imm32','','Valid','Valid',0,'Subtract imm32 from r/m32.'),(1395,'REX.W + 81 /5 id','SUB','r/m64','imm32','','Valid','N.E.',0,'Subtract imm32 signextended\r\nto 64-bits from\r\nr/m64.'),(1396,'83 /5 ib','SUB','r/m16','imm8','','Valid','Valid',0,'Subtract sign-extended imm8\r\nfrom r/m16.'),(1397,'83 /5 ib','SUB','r/m32','imm8','','Valid','Valid',0,'Subtract sign-extended imm8\r\nfrom r/m32.'),(1398,'REX.W + 83 /5 ib','SUB','r/m64','imm8','','Valid','N.E.',0,'Subtract sign-extended imm8\r\nfrom r/m64.'),(1399,'28 /r','SUB','r/m8','r8','','Valid','Valid',0,'Subtract r8 from r/m8.'),(1400,'REX + 28 /r','SUB','r/m8','r8','','Valid','N.E',0,'Subtract r8 from r/m8.'),(1401,'29 /r','SUB','r/m16','r16','','Valid','Valid',0,'Subtract r16 from r/m16.'),(1402,'29 /r','SUB','r/m32','r32','','Valid','Valid',0,'Subtract r32 from r/m32.'),(1403,'REX.W + 29 /r','SUB','r/m64','r32','','Valid','N.E.',0,'Subtract r64 from r/m64.'),(1404,'2A /r','SUB','r8','r/m8','','Valid','Valid',0,'Subtract r/m8 from r8.'),(1405,'REX + 2A /r','SUB','r8','r/m8','','Valid','N.E.',0,'Subtract r/m8 from r8.'),(1406,'2B /r','SUB','r16','r/m16','','Valid','Valid',0,'Subtract r/m16 from r16.'),(1407,'2B /r','SUB','r32','r/m32','','Valid','Valid',0,'Subtract r/m32 from r32.'),(1408,'REX.W + 2B /r','SUB','r64','r/m64','','Valid','N.E.',0,'Subtract r/m64 from r64.'),(1409,'66 0F 5C /r','SUBPD','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed double-precision\r\nfloating-point values in\r\nxmm2/m128 from xmm1.'),(1410,'0F 5C /r','SUBPS','xmm1','xmm2/m128','','Valid','Valid',0,'Subtract packed single-precision\r\nfloating-point values in xmm2/mem\r\nfrom xmm1.'),(1411,'F2 0F 5C /r','SUBSD','xmm1','xmm2/m64','','Valid','Valid',0,'Subtracts the low doubleprecision\r\nfloating-point values in\r\nxmm2/mem64 from xmm1.'),(1412,'F3 0F 5C /r','SUBSS','xmm1','xmm2/m32','','Valid','Valid',0,'Subtract the lower single-precision\r\nfloating-point values in xmm2/m32\r\nfrom xmm1.'),(1413,'0F 01 /7','SWAPGS','','','','Valid','Invalid',0,'Exchanges the current GS base register\r\nvalue with the value contained in MSR\r\naddress C0000102H.'),(1414,'0F 05','SYSCALL','','','','Valid','Invalid',0,'Fast call to privilege level 0\r\nsystem procedures.'),(1415,'0F 34','SYSENTER','','','','Valid','Valid',0,'Fast call to privilege level 0 system\r\nprocedures.'),(1416,'0F 35','SYSEXIT','','','','Valid','Valid',0,'Fast return to privilege level 3 user code.'),(1417,'REX.W + 0F 35','SYSEXIT','','','','Valid','Valid',0,'Fast return to 64-bit mode privilege level 3\r\nuser code.'),(1418,'0F 07','SYSRET','','','','Valid','Invalid',0,'Return from fast system call'),(1419,'A8 ib','TEST','AL','imm8','','Valid','Valid',0,'AND imm8 with AL; set SF, ZF,\r\nPF according to result.'),(1420,'A9 iw','TEST','AX','imm16','','Valid','Valid',0,'AND imm16 with AX; set SF,\r\nZF, PF according to result.'),(1421,'A9 id','TEST','EAX','imm32','','Valid','Valid',0,'AND imm32 with EAX; set SF,\r\nZF, PF according to result.'),(1422,'REX.W + A9 id','TEST','RAX','imm32','','Valid','N.E.',0,'AND imm32 sign-extended to\r\n64-bits with RAX; set SF, ZF,\r\nPF according to result.'),(1423,'F6 /0 ib','TEST','r/m8','imm8','','Valid','Valid',0,'AND imm8 with r/m8; set SF,\r\nZF, PF according to result.'),(1424,'REX + F6 /0 ib','TEST','r/m8','imm8','','Valid','N.E.',0,'AND imm8 with r/m8; set SF,\r\nZF, PF according to result.'),(1425,'F7 /0 iw','TEST','r/m16','imm16','','Valid','Valid',0,'AND imm16 with r/m16; set\r\nSF, ZF, PF according to result.'),(1426,'F7 /0 id','TEST','r/m32','imm32','','Valid','Valid',0,'AND imm32 with r/m32; set\r\nSF, ZF, PF according to result.'),(1427,'REX.W + F7 /0 id','TEST','r/m64','imm32','','Valid','N.E.',0,'AND imm32 sign-extended to\r\n64-bits with r/m64; set SF, ZF,\r\nPF according to result.'),(1428,'84 /r','TEST','r/m8','r8','','Valid','Valid',0,'AND r8 with r/m8; set SF, ZF,\r\nPF according to result.'),(1429,'REX + 84 /r','TEST','r/m8','r8','','Valid','N.E.',0,'AND r8 with r/m8; set SF,\r\nPF according to result.'),(1430,'85 /r','TEST','r/m16','r16','','Valid','Valid',0,'AND r16 with r/m16; set SF,\r\nZF, PF according to result.'),(1431,'85 /r','TEST','r/m32','r32','','Valid','Valid',0,'AND r32 with r/m32; set SF,\r\nZF, PF according to result.'),(1432,'REX.W + 85 /r','TEST','r/m64','r64','','Valid','N.E.',0,'AND r64 with r/m64; set SF,\r\nZF, PF according to result.'),(1433,'66 0F 2E /r','UCOMISD','xmm1','xmm2/m64','','Valid','Valid',0,'Compares (unordered) the low doubleprecision\r\nfloating-point values in\r\nxmm1 and xmm2/m64 and set the\r\nEFLAGS accordingly.'),(1434,'0F 2E /r','UCOMISS','xmm1','xmm2/m32','','Valid','Valid',0,'Compare lower single-precision floatingpoint\r\nvalue in xmm1 register with lower\r\nsingle-precision floating-point value in\r\nxmm2/mem and set the status flags\r\naccordingly.'),(1435,'0F 0B','UD2','','','','Valid','Valid',0,'Raise invalid opcode exception.'),(1436,'66 0F 15 /r','UNPCKHPD','xmm1','xmm2/m128','','Valid','Valid',0,'Unpacks and Interleaves doubleprecision\r\nfloating-point values\r\nfrom high quadwords of xmm1\r\nand xmm2/m128.'),(1437,'0F 15 /r','UNPCKHPS','xmm1','xmm2/m128','','Valid','Valid',0,'Unpacks and Interleaves singleprecision\r\nfloating-point values\r\nfrom high quadwords of xmm1\r\nand xmm2/mem into xmm1.'),(1438,'66 0F 14 /r','UNPCKLPD','xmm1','xmm2/m128','','Valid','Valid',0,'Unpacks and Interleaves doubleprecision\r\nfloating-point values from\r\nlow quadwords of xmm1 and\r\nxmm2/m128.'),(1439,'0F 14 /r','UNPCKLPS','xmm1','xmm2/m128','','Valid','Valid',0,'Unpacks and Interleaves singleprecision\r\nfloating-point values from\r\nlow quadwords of xmm1 and\r\nxmm2/mem into xmm1.'),(1440,'0F 00 /4','VERR','r/m16','','','Valid','Valid',0,'Set ZF=1 if segment specified with\r\nr/m16 can be read.'),(1441,'0F 00 /5','VERW','r/m16','','','Valid','Valid',0,'Set ZF=1 if segment specified with\r\nr/m16 can be written.'),(1442,'9B','WAIT','','','','Valid','Valid',0,'Check pending unmasked floatingpoint\r\nexceptions.'),(1443,'9B','FWAIT','','','','Valid','Valid',0,'Check pending unmasked floatingpoint\r\nexceptions.'),(1444,'0F 09','WBINVD','','','','Valid','Valid',0,'Write back and flush Internal caches;\r\ninitiate writing-back and flushing of\r\nexternal caches.'),(1445,'0F 30','WRMSR','','','','Valid','Valid',0,'Write the value in EDX:EAX to MSR\r\nspecified by ECX.'),(1446,'0F C0 /r','XADD','r/m8','r8','','Valid','Valid',0,'Exchange r8 and r/m8; load\r\nsum into r/m8.'),(1447,'REX + 0F C0 /r','XADD','r/m8','r8','','Valid','N.E.',0,'Exchange r8 and r/m8; load\r\nsum into r/m8.'),(1448,'0F C1 /r','XADD','r/m16','r16','','Valid','Valid',0,'Exchange r16 and r/m16;\r\nload sum into r/m16.'),(1449,'0F C1 /r','XADD','r/m32','r32','','Valid','Valid',0,'Exchange r32 and r/m32;\r\nload sum into r/m32.'),(1450,'REX.W + 0F C1 /r','XADD','r/m64','r64','','Valid','N.E',0,'Exchange r64 and r/m64;\r\nload sum into r/m64.'),(1451,'90+rw','XCHG','AX','r16','','Valid','Valid',0,'Exchange r16 with AX.'),(1452,'90+rw','XCHG','r16','AX','','Valid','Valid',0,'Exchange AX with r16.'),(1453,'90+rd','XCHG','EAX','r32','','Valid','Valid',0,'Exchange r32 with EAX.'),(1454,'REX.W + 90+rd','XCHG','RAX','r64','','Valid','N.E.',0,'Exchange r64 with RAX.'),(1455,'90+rd','XCHG','r32','EAX','','Valid','Valid',0,'Exchange EAX with r32.'),(1456,'REX.W + 90+rd','XCHG','r64','RAX','','Valid','N.E.',0,'Exchange RAX with r64.'),(1457,'86 /r','XCHG','r/m8','r8','','Valid','Valid',0,'Exchange r8 (byte register) with\r\nbyte from r/m8.'),(1458,'REX + 86 /r','XCHG','r/m8','r8','','Valid','N.E.',0,'Exchange r8 (byte register) with\r\nbyte from r/m8.'),(1459,'86 /r','XCHG','r8','r/m8','','Valid','Valid',0,'Exchange byte from r/m8 with\r\nr8 (byte register).'),(1460,'REX + 86 /r','XCHG','r8','r/m8','','Valid','N.E.',0,'Exchange byte from r/m8 with\r\nr8 (byte register).'),(1461,'87 /r','XCHG','r/m16','r16','','Valid','Valid',0,'Exchange r16 with word from\r\nr/m16.'),(1462,'87 /r','XCHG','r16','r/m16','','Valid','Valid',0,'Exchange word from r/m16 with\r\nr16.'),(1463,'87 /r','XCHG','r/m32','r32','','Valid','Valid',0,'Exchange r32 with doubleword\r\nfrom r/m32.'),(1464,'REX.W + 87 /r','XCHG','r/m64','r64','','Valid','N.E.',0,'Exchange r64 with quadword\r\nfrom r/m64.'),(1465,'87 /r','XCHG','r32','r/m32','','Valid','Valid',0,'Exchange doubleword from'),(1466,'REX.W + 87 /r','XCHG','r64','r/m64','','Valid','N.E.',0,'Exchange quadword from r/m64\r\nwith r64.'),(1467,'D7','XLAT','m8','','','Valid','Valid',0,'Set AL to memory byte DS:[(E)BX +\r\nunsigned AL].'),(1468,'D7','XLATB','','','','Valid','Valid',0,'Set AL to memory byte DS:[(E)BX +\r\nunsigned AL].'),(1469,'REX.W + D7','XLATB','','','','Valid','N.E.',0,'Set AL to memory byte [RBX +\r\nunsigned AL].'),(1470,'34 ib','XOR','AL','imm8','','Valid','Valid',0,'AL XOR imm8.'),(1471,'35 iw','XOR','AX','imm16','','Valid','Valid',0,'AX XOR imm16.'),(1472,'35 id','XOR','EAX','imm32','','Valid','Valid',0,'EAX XOR imm32.'),(1473,'REX.W + 35 id','XOR','RAX','imm32','','Valid','N.E.',0,'RAX XOR imm32 (signextended).'),(1474,'80 /6 ib','XOR','r/m8','imm8','','Valid','Valid',0,'r/m8 XOR imm8.'),(1475,'REX + 80 /6 ib','XOR','r/m8','imm8','','Valid','N.E.',0,'r/m8 XOR imm8.'),(1476,'81 /6 iw','XOR','r/m16','imm16','','Valid','Valid',0,'r/m16 XOR imm16.'),(1477,'81 /6 id','XOR','r/m32','imm32','','Valid','Valid',0,'r/m32 XOR imm32.'),(1478,'REX.W + 81 /6 id','XOR','r/m64','imm32','','Valid','N.E.',0,'r/m64 XOR imm32 (signextended).'),(1479,'83 /6 ib','XOR','r/m16','imm8','','Valid','Valid',0,'r/m16 XOR imm8 (signextended).'),(1480,'83 /6 ib','XOR','r/m32','imm8','','Valid','Valid',0,'r/m32 XOR imm8 (signextended).'),(1481,'REX.W + 83 /6 ib','XOR','r/m64','imm8','','Valid','N.E.',0,'r/m64 XOR imm8 (signextended).'),(1482,'30 /r','XOR','r/m8','r8','','Valid','Valid',0,'r/m8 XOR r8.'),(1483,'REX + 30 /r','XOR','r/m8','r8','','Valid','N.E.',0,'r/m8 XOR r8.'),(1484,'31 /r','XOR','r/m16','r16','','Valid','Valid',0,'r/m16 XOR r16.'),(1485,'31 /r','XOR','r/m32','r32','','Valid','Valid',0,'r/m32 XOR r32.'),(1486,'REX.W + 31 /r','XOR','r/m64','r64','','Valid','N.E.',0,'r/m64 XOR r64.'),(1487,'32 /r','XOR','r8','r/m8','','Valid','Valid',0,'r8 XOR r/m8.'),(1488,'REX + 32 /r','XOR','r8','r/m8','','Valid','N.E.',0,'r8 XOR r/m8.'),(1489,'33 /r','XOR','r16','r/m16','','Valid','Valid',0,'r16 XOR r/m16.'),(1490,'33 /r','XOR','r32','r/m32','','Valid','Valid',0,'r32 XOR r/m32.'),(1491,'REX.W + 33 /r','XOR','r64','r/m64','','Valid','N.E',0,'r64 XOR r/m64.'),(1492,'66 0F 57 /r','XORPD','xmm1','xmm2/m128','','Valid','Valid',0,'Bitwise exclusive-OR of\r\nxmm2/m128 and xmm1.'),(1494,'0F 01 C1','VMCALL','','','','','',1,'Call to VM monitor by causing VM exit.'),(1495,'66 0F C7 /6','VMCLEAR','m64','','','','',1,'Copy VMCS data to VMCS region in memory.'),(1496,'0F 01 C2','VMLAUNCH','','','','','',1,'Launch virtual machine managed by current VMCS.'),(1497,'0F 01 C3','VMRESUME','','','','','',1,'Resume virtual machine managed by current VMCS.'),(1498,'0F C7 /6','VMPTRLD','m64','','','','',1,'Loads the current VMCS pointer from memory.'),(1499,'0F C7 /7','VMPTRST','m64','','','','',1,'Stores the current VMCS pointer into memory.'),(1500,'0F 78','VMREAD','r/m64','r64','','','',1,'Reads a specified VMCS field (in 64-bit mode).'),(1501,'0F 78','VMREAD','r/m32','r32','','','',1,'Reads a specified VMCS field (outside 64-bit mode).'),(1502,'0F 79','VMWRITE','r64','r/m64','','','',1,'Writes.a specified VMCS field (in 64-bit mode)'),(1503,'0F 79','VMWRITE','r32','r/m32','','','',1,'Writes.a specified VMCS field (outside 64-bit mode)'),(1504,'0F 01 C4','VMXOFF','','','','','',1,'Leaves VMX operation.'),(1505,'F3 0F C7 /6','VMXON','m64','','','','',1,'Enter VMX root operation.'); UNLOCK TABLES; /*!40000 ALTER TABLE `IA-x86` ENABLE KEYS */; /*!40103 SET TIME_ZONE=@OLD_TIME_ZONE */; /*!40101 SET SQL_MODE=@OLD_SQL_MODE */; /*!40014 SET FOREIGN_KEY_CHECKS=@OLD_FOREIGN_KEY_CHECKS */; /*!40014 SET UNIQUE_CHECKS=@OLD_UNIQUE_CHECKS */; /*!40101 SET CHARACTER_SET_CLIENT=@OLD_CHARACTER_SET_CLIENT */; /*!40101 SET CHARACTER_SET_RESULTS=@OLD_CHARACTER_SET_RESULTS */; /*!40101 SET COLLATION_CONNECTION=@OLD_COLLATION_CONNECTION */; /*!40111 SET SQL_NOTES=@OLD_SQL_NOTES */;